2018-02-08 15:27:53 +08:00
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/*
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* File : start_gcc.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2013-2018, RT-Thread Development Team
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*/
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.equ MODE_USR, 0x10
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.equ MODE_FIQ, 0x11
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.equ MODE_IRQ, 0x12
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.equ MODE_SVC, 0x13
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.equ MODE_ABT, 0x17
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.equ MODE_UND, 0x1B
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.equ MODE_SYS, 0x1F
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.equ MODEMASK, 0x1F
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.equ NOINT, 0xC0
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.equ I_BIT, 0x80
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.equ F_BIT, 0x40
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.equ UND_STACK_SIZE, 0x00000100
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.equ SVC_STACK_SIZE, 0x00000100
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.equ ABT_STACK_SIZE, 0x00000100
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.equ FIQ_STACK_SIZE, 0x00000100
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.equ IRQ_STACK_SIZE, 0x00000100
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.equ SYS_STACK_SIZE, 0x00000100
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/*
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***************************************
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* Interrupt vector table
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***************************************
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*/
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.section .vectors
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.code 32
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.global system_vectors
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system_vectors:
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ldr pc, _vector_reset
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ldr pc, _vector_undef
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ldr pc, _vector_swi
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ldr pc, _vector_pabt
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ldr pc, _vector_dabt
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ldr pc, _vector_resv
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ldr pc, _vector_irq
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ldr pc, _vector_fiq
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_vector_reset:
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.word reset
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_vector_undef:
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.word vector_undef
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_vector_swi:
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2018-12-10 16:31:33 +08:00
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.word SVC_Handler
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2018-02-08 15:27:53 +08:00
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_vector_pabt:
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.word vector_pabt
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_vector_dabt:
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.word vector_dabt
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_vector_resv:
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.word vector_resv
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_vector_irq:
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.word vector_irq
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_vector_fiq:
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.word vector_fiq
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.balignl 16,0xdeadbeef
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/*
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***************************************
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* Stack and Heap Definitions
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***************************************
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*/
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.section .data
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.space UND_STACK_SIZE
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.align 3
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.global und_stack_start
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und_stack_start:
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.space ABT_STACK_SIZE
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.align 3
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.global abt_stack_start
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abt_stack_start:
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.space FIQ_STACK_SIZE
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.align 3
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.global fiq_stack_start
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fiq_stack_start:
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.space IRQ_STACK_SIZE
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.align 3
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.global irq_stack_start
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irq_stack_start:
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.skip SYS_STACK_SIZE
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.align 3
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.global sys_stack_start
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sys_stack_start:
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.space SVC_STACK_SIZE
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.align 3
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.global svc_stack_start
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svc_stack_start:
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/*
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***************************************
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* Startup Code
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***************************************
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*/
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.section .text
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.global reset
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reset:
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/* Enter svc mode and mask interrupts */
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mrs r0, cpsr
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bic r0, r0, #MODEMASK
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orr r0, r0, #MODE_SVC|NOINT
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msr cpsr_cxsf, r0
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/* init cpu */
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bl cpu_init_crit
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/* todo:copyself to link address */
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/* Copy vector to the correct address */
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ldr r0, =system_vectors
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mrc p15, 0, r2, c1, c0, 0
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ands r2, r2, #(1 << 13)
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ldreq r1, =0x00000000
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ldrne r1, =0xffff0000
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ldmia r0!, {r2-r8, r10}
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stmia r1!, {r2-r8, r10}
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ldmia r0!, {r2-r8, r10}
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stmia r1!, {r2-r8, r10}
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/* turn off the watchdog */
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ldr r0, =0x01C20CB8
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mov r1, #0x0
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str r1, [r0]
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/* mask all IRQs source */
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ldr r1, =0xffffffff
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ldr r0, =0x01C20430
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str r1, [r0], #0x04
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str r1, [r0]
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/* Call low level init function */
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ldr sp, =svc_stack_start
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ldr r0, =rt_low_level_init
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blx r0
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/* init stack */
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bl stack_setup
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/* clear bss */
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mov r0, #0
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ldr r1, =__bss_start
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ldr r2, =__bss_end
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bss_clear_loop:
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cmp r1, r2
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strlo r0, [r1], #4
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blo bss_clear_loop
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/* call c++ constructors of global objects */
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/*
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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*/
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/* start RT-Thread Kernel */
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ldr pc, _rtthread_startup
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_rtthread_startup:
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.word rtthread_startup
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cpu_init_crit:
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/* invalidate I/D caches */
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0
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mcr p15, 0, r0, c8, c7, 0
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/* disable MMU stuff and caches */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300
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bic r0, r0, #0x00000087
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orr r0, r0, #0x00000002
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orr r0, r0, #0x00001000
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mcr p15, 0, r0, c1, c0, 0
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bx lr
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stack_setup:
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/* Setup Stack for each mode */
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mrs r0, cpsr
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bic r0, r0, #MODEMASK
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orr r1, r0, #MODE_UND|NOINT
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msr cpsr_cxsf, r1
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ldr sp, =und_stack_start
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orr r1, r0, #MODE_ABT|NOINT
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msr cpsr_cxsf, r1
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ldr sp, =abt_stack_start
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orr r1, r0, #MODE_IRQ|NOINT
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msr cpsr_cxsf, r1
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ldr sp, =irq_stack_start
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orr r1, r0, #MODE_FIQ|NOINT
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msr cpsr_cxsf, r1
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ldr sp, =fiq_stack_start
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orr r1, r0, #MODE_SYS|NOINT
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msr cpsr_cxsf,r1
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ldr sp, =sys_stack_start
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orr r1, r0, #MODE_SVC|NOINT
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msr cpsr_cxsf, r1
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ldr sp, =svc_stack_start
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bx lr
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/*
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***************************************
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* exception handlers
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***************************************
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*/
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.global rt_hw_trap_udef
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.global rt_hw_trap_swi
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.global rt_hw_trap_pabt
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.global rt_hw_trap_dabt
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.global rt_hw_trap_resv
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.global rt_hw_trap_irq
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.global rt_hw_trap_fiq
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.global rt_interrupt_enter
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.global rt_interrupt_leave
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.global rt_thread_switch_interrupt_flag
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.global rt_interrupt_from_thread
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.global rt_interrupt_to_thread
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/* Interrupt */
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.align 5
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vector_fiq:
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stmfd sp!,{r0-r7,lr}
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bl rt_hw_trap_fiq
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ldmfd sp!,{r0-r7,lr}
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subs pc, lr, #4
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.align 5
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vector_irq:
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stmfd sp!, {r0-r12,lr}
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bl rt_interrupt_enter
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bl rt_hw_trap_irq
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bl rt_interrupt_leave
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ldr r0, =rt_thread_switch_interrupt_flag
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ldr r1, [r0]
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cmp r1, #1
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beq rt_hw_context_switch_interrupt_do
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ldmfd sp!, {r0-r12,lr}
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subs pc, lr, #4
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rt_hw_context_switch_interrupt_do:
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mov r1, #0
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str r1, [r0]
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mov r1, sp
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add sp, sp, #4*4
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ldmfd sp!, {r4-r12,lr}
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mrs r0, spsr
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sub r2, lr, #4
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msr cpsr_c, #I_BIT|F_BIT|MODE_SVC
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stmfd sp!, {r2}
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stmfd sp!, {r4-r12,lr}
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ldmfd r1, {r1-r4}
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stmfd sp!, {r1-r4}
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stmfd sp!, {r0}
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ldr r4, =rt_interrupt_from_thread
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ldr r5, [r4]
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str sp, [r5]
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ldr r6, =rt_interrupt_to_thread
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ldr r6, [r6]
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ldr sp, [r6]
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ldmfd sp!, {r4}
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msr spsr_cxsf, r4
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ldmfd sp!, {r0-r12,lr,pc}^
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/* Exception */
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.macro push_svc_reg
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sub sp, sp, #17 * 4
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stmia sp, {r0 - r12}
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mov r0, sp
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mrs r6, spsr
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str lr, [r0, #15*4]
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str r6, [r0, #16*4]
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str sp, [r0, #13*4]
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str lr, [r0, #14*4]
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.endm
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2018-12-10 16:31:33 +08:00
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.align 5
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.weak SVC_Handler
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SVC_Handler:
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2018-02-08 15:27:53 +08:00
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vector_swi:
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push_svc_reg
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bl rt_hw_trap_swi
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b .
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.align 5
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vector_undef:
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push_svc_reg
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bl rt_hw_trap_udef
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b .
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.align 5
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vector_pabt:
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push_svc_reg
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bl rt_hw_trap_pabt
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b .
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.align 5
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vector_dabt:
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push_svc_reg
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bl rt_hw_trap_dabt
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b .
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.align 5
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vector_resv:
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push_svc_reg
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bl rt_hw_trap_resv
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b .
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