85 lines
3.5 KiB
Plaintext
85 lines
3.5 KiB
Plaintext
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/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* ESP32-C3 Linker Script Memory Layout
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* This file describes the memory layout (memory blocks) by virtual memory addresses.
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* This linker script is passed through the C preprocessor to include configuration options.
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* Please use preprocessor features sparingly!
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* Restrict to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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/*
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* Automatically generated file. DO NOT EDIT.
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* Espressif IoT Development Framework (ESP-IDF) Configuration Header
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*/
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/* List of deprecated options */
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/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* CPU instruction prefetch padding size for flash mmap scenario */
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_esp_flash_mmap_prefetch_pad_size = 16;
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/* CPU instruction prefetch padding size for memory protection scenario */
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_esp_memprot_prefetch_pad_size = 16;
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/* Memory alignment size for PMS */
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_esp_memprot_align_size = 512;
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_esp_mmu_block_size = (0x10000);
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/**
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* physical memory is mapped twice to the vritual address (IRAM and DRAM).
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* `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
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*/
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MEMORY
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{
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/**
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* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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* of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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* are connected to the data port of the CPU and eg allow byte-wise access.
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*/
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/* IRAM for PRO CPU. */
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iram0_0_seg (RX) : org = (0x4037C000 + 0x4000), len = 0x403CF600 - (0x4037C000 - 0x3FC7C000) - (0x3FC7C000 + 0x4000)
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/* Flash mapped instruction data */
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iram0_2_seg (RX) : org = 0x42000020, len = 0x800000-0x20
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/**
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* (0x20 offset above is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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/**
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* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
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*/
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dram0_0_seg (RW) : org = (0x3FC7C000 + 0x4000), len = 0x403CF600 - (0x4037C000 - 0x3FC7C000) - (0x3FC7C000 + 0x4000)
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20
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/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
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/**
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* RTC fast memory (executable). Persists over deep sleep.
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*/
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rtc_iram_seg(RWX) : org = 0x50000000, len = 0x2000 - 0
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}
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_static_data_end = _bss_end;
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x40000000;
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_data_seg_org = ORIGIN(rtc_data_seg);
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/**
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* The lines below define location alias for .rtc.data section
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* As C3 only has RTC fast memory, this is not configurable like on other targets
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*/
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REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
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REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
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REGION_ALIAS("rtc_data_location", rtc_iram_seg );
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REGION_ALIAS("default_code_seg", iram0_2_seg);
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REGION_ALIAS("default_rodata_seg", drom0_0_seg);
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/**
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* If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
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* also be first in the segment.
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*/
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ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
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".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
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