267 lines
9.4 KiB
C
267 lines
9.4 KiB
C
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#ifndef __CVI_PWM_H__
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#define __CVI_PWM_H__
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#include <stdio.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define __IM volatile const /*! Defines 'read only' structure member permissions */
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#define __OM volatile /*! Defines 'write only' structure member permissions */
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#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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#define CVI_PWM0_BASE 0x03060000
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#define CVI_PWM1_BASE 0x03061000
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#define CVI_PWM2_BASE 0x03062000
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#define CVI_PWM3_BASE 0x03063000
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typedef enum {
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PWM_CHANNEL_0 = 0U,
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PWM_CHANNEL_1,
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PWM_CHANNEL_2,
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PWM_CHANNEL_3,
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PWM_CHANNEL_4,
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PWM_CHANNEL_5,
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PWM_CHANNEL_6,
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PWM_CHANNEL_7,
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PWM_CHANNEL_8,
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PWM_CHANNEL_9,
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PWM_CHANNEL_10,
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PWM_CHANNEL_11,
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PWM_CHANNEL_12,
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PWM_CHANNEL_13,
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PWM_CHANNEL_14,
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PWM_CHANNEL_15,
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PWM_CHANNEL_NUM
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} cvi_pwm_channel_t;
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struct cvi_pwm_regs_t {
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uint32_t HLPERIOD0;
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uint32_t PERIOD0;
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uint32_t HLPERIOD1;
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uint32_t PERIOD1;
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uint32_t HLPERIOD2;
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uint32_t PERIOD2;
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uint32_t HLPERIOD3;
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uint32_t PERIOD3;
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uint32_t CAP_FREQNUM;
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uint32_t CAP_FREQDATA;
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uint32_t POLARITY;
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uint32_t PWMSTART;
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uint32_t PWMDONE;
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uint32_t PWMUPDATE;
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uint32_t PCOUNT0;
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uint32_t PCOUNT1;
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uint32_t PCOUNT2;
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uint32_t PCOUNT3;
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uint32_t PULSECOUNT0;
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uint32_t PULSECOUNT1;
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uint32_t PULSECOUNT2;
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uint32_t PULSECOUNT3;
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uint32_t SHIFTCOUNT0;
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uint32_t SHIFTCOUNT1;
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uint32_t SHIFTCOUNT2;
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uint32_t SHIFTCOUNT3;
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uint32_t SHIFTSTART;
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uint32_t CAP_FREQEN;
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uint32_t CAP_FREQDONE_NUM;
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uint32_t PWM_OE;
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};
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static struct cvi_pwm_regs_t cv182x_pwm_reg = {
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.HLPERIOD0 = 0x0,
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.PERIOD0 = 0x4,
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.HLPERIOD1 = 0x8,
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.PERIOD1 = 0xc,
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.HLPERIOD2 = 0x10,
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.PERIOD2 = 0x14,
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.HLPERIOD3 = 0x18,
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.PERIOD3 = 0x1c,
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.CAP_FREQNUM = 0x20,
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.CAP_FREQDATA = 0x24,
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.POLARITY = 0x40,
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.PWMSTART = 0x44,
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.PWMDONE = 0x48,
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.PWMUPDATE = 0x4c,
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.PCOUNT0 = 0x50,
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.PCOUNT1 = 0x54,
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.PCOUNT2 = 0x58,
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.PCOUNT3 = 0x5c,
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.PULSECOUNT0 = 0x60,
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.PULSECOUNT1 = 0x64,
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.PULSECOUNT2 = 0x68,
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.PULSECOUNT3 = 0x6c,
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.SHIFTCOUNT0 = 0x80,
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.SHIFTCOUNT1 = 0x84,
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.SHIFTCOUNT2 = 0x88,
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.SHIFTCOUNT3 = 0x8c,
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.SHIFTSTART = 0x90,
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.CAP_FREQEN = 0x9c,
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.CAP_FREQDONE_NUM = 0xC0,
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.PWM_OE = 0xd0,
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};
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static struct cvi_pwm_regs_t *cvi_pwm_reg = &cv182x_pwm_reg;
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#define PWM_HLPERIOD0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD0))
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#define PWM_PERIOD0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD0))
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#define PWM_HLPERIOD1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD1))
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#define PWM_PERIOD1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD1))
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#define PWM_HLPERIOD2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD2))
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#define PWM_PERIOD2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD2))
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#define PWM_HLPERIOD3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD3))
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#define PWM_PERIOD3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD3))
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#define PWM_HLPERIODX(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD0 + (_ch_ << 3)))
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#define PWM_PERIODX(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD0 * (1 + (_ch_ << 1))))
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#define CAP_FREQNUM(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQNUM + _ch_ * 8))
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#define CAP_FREQDATA(reg_base, _ch_) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQDATA + _ch_ * 8))
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#define PWM_POLARITY(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->POLARITY))
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#define PWM_PWMSTART(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMSTART))
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#define PWM_PWMDONE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMDONE))
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#define PWM_PWMUPDATE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMUPDATE))
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#define PWM_PCOUNT0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT0))
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#define PWM_PCOUNT1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT1))
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#define PWM_PCOUNT2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT2))
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#define PWM_PCOUNT3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT3))
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#define PWM_PULSECOUNT0(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT0))
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#define PWM_PULSECOUNT1(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT1))
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#define PWM_PULSECOUNT2(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT2))
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#define PWM_PULSECOUNT3(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT3))
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#define PWM_SHIFTCOUNT0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT0))
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#define PWM_SHIFTCOUNT1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT1))
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#define PWM_SHIFTCOUNT2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT2))
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#define PWM_SHIFTCOUNT3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT3))
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#define PWM_SHIFTSTART(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTSTART))
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#define CAP_FREQEN(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQEN))
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#define CAP_FREQDONE_NUM(reg_base, _ch_) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQDONE_NUM + _ch_ * 4))
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#define PWM_PWM_OE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWM_OE))
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/*! PWM Configure Register, offset: 0x00 */
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#define CVI_PWM_HIGH_PERIOD_Pos (0U)
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#define CVI_PWM_HIGH_PERIOD_Msk (0xffffffff)
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#define CVI_PWM_PERIOD_Pos (0U)
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#define CVI_PWM_PERIOD_Msk (0xffffffff)
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#define CVI_PWM_POLARITY_CH_Pos(_ch_) (_ch_)
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#define CVI_PWM_POLARITY_CH_Msk(_ch_) (1U << CVI_PWM_POLARITY_CH_Pos(_ch_))
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#define CVI_PWM_POLARITY_CH_HIGH(_ch_) CVI_PWM_POLARITY_CH_Msk(_ch_)
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#define CVI_PWM_START_CH_Pos(_ch_) (_ch_)
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#define CVI_PWM_START_CH_Msk(_ch_) (1U << CVI_PWM_START_CH_Pos(_ch_))
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#define CVI_PWM_START_CH_EN(_ch_) CVI_PWM_START_CH_Msk(_ch_)
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#define CVI_PWM_OUTPUT_CH_Pos(_ch_) (_ch_)
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#define CVI_PWM_OUTPUT_CH_Msk(_ch_) (1U << CVI_PWM_OUTPUT_CH_Pos(_ch_))
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#define CVI_PWM_OUTPUT_CH_EN(_ch_) CVI_PWM_OUTPUT_CH_Msk(_ch_)
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#define CVI_CAP_FREQNUM_CH_Pos (0U)
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#define CVI_CAP_FREQNUM_CH_Msk (0xffffffff)
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#define CVI_CAP_FREQEN_Pos(_ch_) (_ch_)
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#define CVI_CAP_FREQEN_Msk(_ch_) (1U << CVI_CAP_FREQEN_Pos(_ch_))
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#define CVI_CAP_FREQEN(_ch_) CVI_CAP_FREQEN_Msk(_ch_)
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#define CVI_CAP_FREQDONE_NUM_Poa (0U)
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#define CVI_CAP_FREQDONE_NUM_Msk (0xffffffff)
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#define CVI_CAP_FREQDATA_pos (0U)
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#define CVI_CAP_FREQDATA_msk (0xffffffff)
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static inline void cvi_pwm_set_high_period_ch(unsigned long reg_base, uint32_t ch, unsigned long long value)
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{
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PWM_HLPERIODX(reg_base, ch) = value;
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}
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static inline unsigned long long cvi_pwm_get_high_period_ch(unsigned long reg_base, uint32_t ch)
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{
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return PWM_HLPERIODX(reg_base, ch);
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}
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static inline void cvi_pwm_set_period_ch(unsigned long reg_base, uint32_t ch, unsigned long long value)
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{
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PWM_PERIODX(reg_base, ch) = value;
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}
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static inline unsigned long long cvi_pwm_get_period_ch(unsigned long reg_base, uint32_t ch)
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{
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return PWM_PERIODX(reg_base, ch);
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}
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static inline void cvi_pwm_set_polarity_high_ch(unsigned long reg_base, uint32_t ch)
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{
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PWM_POLARITY(reg_base) |= CVI_PWM_POLARITY_CH_HIGH(ch);
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}
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static inline void cvi_pwm_set_polarity_low_ch(unsigned long reg_base, uint32_t ch)
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{
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PWM_POLARITY(reg_base) &= ~CVI_PWM_POLARITY_CH_HIGH(ch);
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}
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static inline uint32_t cvi_pwm_get_polarity(unsigned long reg_base, uint32_t ch)
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{
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return (PWM_POLARITY(reg_base) & CVI_PWM_POLARITY_CH_Msk(ch));
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}
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static inline void cvi_pwm_start_en_ch(unsigned long reg_base, uint32_t ch)
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{
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PWM_PWMSTART(reg_base) |= CVI_PWM_START_CH_EN(ch);
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}
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static inline void cvi_pwm_start_dis_ch(unsigned long reg_base, uint32_t ch)
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{
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PWM_PWMSTART(reg_base) &= ~CVI_PWM_START_CH_EN(ch);
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}
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static inline void cvi_pwm_output_en_ch(unsigned long reg_base, uint32_t ch)
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{
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PWM_PWM_OE(reg_base) |= CVI_PWM_OUTPUT_CH_EN(ch);
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}
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static inline void cvi_pwm_input_en_ch(unsigned long reg_base, uint32_t ch)
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{
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PWM_PWM_OE(reg_base) &= ~CVI_PWM_OUTPUT_CH_EN(ch);
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}
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static inline void cvi_cap_set_freqnum_ch(unsigned long reg_base, uint32_t ch, uint32_t value)
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{
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CAP_FREQNUM(reg_base, ch) = value;
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}
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static inline void cvi_cap_freq_en_ch(unsigned long reg_base, uint32_t ch)
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{
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CAP_FREQEN(reg_base) |= CVI_CAP_FREQEN(ch);
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}
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static inline void cvi_cap_freq_dis_ch(unsigned long reg_base, uint32_t ch)
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{
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CAP_FREQEN(reg_base) &= ~CVI_CAP_FREQEN(ch);
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}
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static inline uint32_t cvi_cap_get_freq_done_num_ch(unsigned long reg_base, uint32_t ch)
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{
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return CAP_FREQDONE_NUM(reg_base, ch);
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}
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static inline uint32_t cvi_cap_get_freq_data_ch(unsigned long reg_base, uint32_t ch)
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{
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return CAP_FREQDATA(reg_base, ch);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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