2021-10-06 16:50:57 +08:00
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/* generated vector header file - do not edit */
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#ifndef VECTOR_DATA_H
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#define VECTOR_DATA_H
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/* Number of interrupts allocated */
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#ifndef VECTOR_DATA_IRQ_COUNT
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2021-11-03 20:40:06 +08:00
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#define VECTOR_DATA_IRQ_COUNT (5)
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2021-10-06 16:50:57 +08:00
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#endif
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/* ISR prototypes */
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void sci_uart_rxi_isr(void);
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void sci_uart_txi_isr(void);
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void sci_uart_tei_isr(void);
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void sci_uart_eri_isr(void);
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2021-11-03 20:40:06 +08:00
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void r_icu_isr(void);
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2021-10-06 16:50:57 +08:00
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/* Vector table allocations */
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#define VECTOR_NUMBER_SCI7_RXI ((IRQn_Type) 0) /* SCI7 RXI (Received data full) */
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#define VECTOR_NUMBER_SCI7_TXI ((IRQn_Type) 1) /* SCI7 TXI (Transmit data empty) */
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#define VECTOR_NUMBER_SCI7_TEI ((IRQn_Type) 2) /* SCI7 TEI (Transmit end) */
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#define VECTOR_NUMBER_SCI7_ERI ((IRQn_Type) 3) /* SCI7 ERI (Receive error) */
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2021-11-03 20:40:06 +08:00
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#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type) 4) /* ICU IRQ0 (External pin interrupt 0) */
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2021-10-06 16:50:57 +08:00
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typedef enum IRQn {
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Reset_IRQn = -15,
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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MemoryManagement_IRQn = -12,
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BusFault_IRQn = -11,
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UsageFault_IRQn = -10,
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SecureFault_IRQn = -9,
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SVCall_IRQn = -5,
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DebugMonitor_IRQn = -4,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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SCI7_RXI_IRQn = 0, /* SCI7 RXI (Received data full) */
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SCI7_TXI_IRQn = 1, /* SCI7 TXI (Transmit data empty) */
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SCI7_TEI_IRQn = 2, /* SCI7 TEI (Transmit end) */
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SCI7_ERI_IRQn = 3, /* SCI7 ERI (Receive error) */
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2021-11-03 20:40:06 +08:00
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ICU_IRQ0_IRQn = 4, /* ICU IRQ0 (External pin interrupt 0) */
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2021-10-06 16:50:57 +08:00
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} IRQn_Type;
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2022-01-09 20:19:55 +08:00
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#endif /* VECTOR_DATA_H */
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