120 lines
2.4 KiB
C
120 lines
2.4 KiB
C
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Email: opensource_embedded@phytium.com.cn
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*
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* Change Logs:
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* Date Author Notes
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* 2023-04-27 huanghe first version
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*
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*/
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#include "rtconfig.h"
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#include <board.h>
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#include <mmu.h>
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/* mmu config */
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#ifdef RT_USING_SMART
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#if defined(TARGET_ARMV8_AARCH64)
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struct mem_desc platform_mem_desc[] =
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{
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{ KERNEL_VADDR_START,
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KERNEL_VADDR_START + 0x0fffffff,
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(rt_size_t)ARCH_MAP_FAILED,
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NORMAL_MEM
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}
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};
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#else
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struct mem_desc platform_mem_desc[] =
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{
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{ KERNEL_VADDR_START,
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KERNEL_VADDR_START + 0x10000000,
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(rt_size_t)ARCH_MAP_FAILED,
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NORMAL_MEM
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}
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};
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#endif
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const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
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#else
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/* mmu config */
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struct mem_desc platform_mem_desc[] =
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{
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{
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0x80000000,
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0xFFFFFFFF,
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0x80000000,
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DDR_MEM
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},
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{
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0, //< QSPI
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0x1FFFFFFF,
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0,
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DEVICE_MEM
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},
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{
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0x20000000, //<! LPC
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0x27FFFFFF,
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0x20000000,
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DEVICE_MEM
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},
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{
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FT_DEV_BASE_ADDR, //<! Device register
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FT_DEV_END_ADDR,
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FT_DEV_BASE_ADDR,
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DEVICE_MEM
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},
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{
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0x30000000, //<! debug
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0x39FFFFFF,
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0x30000000,
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DEVICE_MEM
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},
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{
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0x3A000000, //<! Internal register space in the on-chip network
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0x3AFFFFFF,
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0x3A000000,
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DEVICE_MEM
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},
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{
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FT_PCI_CONFIG_BASEADDR,
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FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
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FT_PCI_CONFIG_BASEADDR,
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DEVICE_MEM
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},
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{
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FT_PCI_IO_CONFIG_BASEADDR,
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FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
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FT_PCI_IO_CONFIG_BASEADDR,
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DEVICE_MEM
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},
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{
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FT_PCI_MEM32_BASEADDR,
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FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
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FT_PCI_MEM32_BASEADDR,
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DEVICE_MEM
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}
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#if defined(TARGET_ARMV8_AARCH64)
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{
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0x1000000000,
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0x1000000000 + 0x1000000000,
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0x1000000000,
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DEVICE_MEM
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},
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{
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0x2000000000,
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0x2000000000 + 0x2000000000,
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0x2000000000,
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NORMAL_MEM
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},
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#endif
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};
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const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
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#endif
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