565 lines
17 KiB
C
565 lines
17 KiB
C
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/*
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* File : drv_gpio.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2018-02-08 RT-Thread the first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "drv_gpio.h"
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#include "interrupt.h"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME "[GPIO]"
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#define DBG_LEVEL DBG_WARNING
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#define DBG_COLOR
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#include <rtdbg.h>
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#define readl(addr) (*(volatile unsigned int *)(addr))
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#define writel(value,addr) (*(volatile unsigned int *)(addr) = (value))
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// Todo: add RT_ASSERT.
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/*********************************************************
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** IO
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*********************************************************/
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int gpio_set_func(enum gpio_port port, enum gpio_pin pin, rt_uint8_t func)
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{
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rt_uint32_t addr;
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rt_uint32_t offset;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_A <= port) && (port < GPIO_PORT_NUM));
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RT_ASSERT((GPIO_PIN_0 <= pin) && (pin < GPIO_PIN_NUM));
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if (func & 0x8)
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{
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dbg_log(DBG_WARNING, "[line]:%d There is a warning with parameter input\n", __LINE__);
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return RT_EINVAL;
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}
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addr = GPIOn_CFG_ADDR(port) + (pin / 8) * 4;
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offset = (pin % 8) * 4;
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data = readl(addr);
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data &= ~(0x7 << offset);
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data |= func << offset;
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writel(data, addr);
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dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr));
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return RT_EOK;
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}
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int gpio_set_value(enum gpio_port port, enum gpio_pin pin, rt_uint8_t value)
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{
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rt_uint32_t addr;
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rt_uint32_t offset;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_A <= port) && (port < GPIO_PORT_NUM));
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RT_ASSERT((GPIO_PIN_0 <= pin) && (pin < GPIO_PIN_NUM));
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if (value & 0xE)
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{
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dbg_log(DBG_WARNING, "[line]:%d There is a warning with parameter input\n", __LINE__);
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return RT_EINVAL;
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}
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addr = GPIOn_DATA_ADDR(port);
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offset = pin;
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data = readl(addr);
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data &= ~(0x1 << offset);
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data |= value << offset;
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writel(data, addr);
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dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr));
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return RT_EOK;
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}
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int gpio_get_value(enum gpio_port port, enum gpio_pin pin)
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{
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rt_uint32_t addr;
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rt_uint32_t offset;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_A <= port) && (port < GPIO_PORT_NUM));
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RT_ASSERT((GPIO_PIN_0 <= pin) && (pin < GPIO_PIN_NUM));
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addr = GPIOn_DATA_ADDR(port);
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offset = pin;
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data = readl(addr);
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dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr));
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return (data >> offset) & 0x01;
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}
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int gpio_set_pull_mode(enum gpio_port port, enum gpio_pin pin, enum gpio_pull pull)
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{
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rt_uint32_t addr;
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rt_uint32_t offset;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_A <= port) && (port < GPIO_PORT_NUM));
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RT_ASSERT((GPIO_PIN_0 <= pin) && (pin < GPIO_PIN_NUM));
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if (pull & 0xC)
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{
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dbg_log(DBG_WARNING, "[line]:%d There is a warning with parameter input\n", __LINE__);
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return RT_EINVAL;
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}
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addr = GPIOn_PUL_ADDR(port);
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addr += pin > GPIO_PIN_15 ? 0x4 : 0x0;
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offset = (pin & 0xf) << 1;
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data = readl(addr);
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data &= ~(0x3 << offset);
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data |= pull << offset;
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writel(data, addr);
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dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr));
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return RT_EOK;
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}
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int gpio_set_drive_level(enum gpio_port port, enum gpio_pin pin, enum gpio_drv_level level)
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{
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volatile rt_uint32_t addr;
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rt_uint32_t offset;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_A <= port) && (port < GPIO_PORT_NUM));
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RT_ASSERT((GPIO_PIN_0 <= pin) && (pin < GPIO_PIN_NUM));
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if (level & 0xC)
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{
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dbg_log(DBG_WARNING, "[line]:%d There is a warning with parameter input\n", __LINE__);
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return RT_EINVAL;
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}
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addr = GPIOn_DRV_ADDR(port);
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addr += pin > GPIO_PIN_15 ? 0x4 : 0x0;
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offset = (pin & 0xf) << 1;
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data = readl(addr);
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data &= ~(0x3 << offset);
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data |= level << offset;
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writel(data, addr);
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dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr));
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return RT_EOK;
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}
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void gpio_direction_input(enum gpio_port port, enum gpio_pin pin)
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{
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volatile rt_uint32_t addr;
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rt_uint32_t offset;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_A <= port) && (port < GPIO_PORT_NUM));
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RT_ASSERT((GPIO_PIN_0 <= pin) && (pin < GPIO_PIN_NUM));
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addr = GPIOn_CFG_ADDR(port) + (pin / 8) * 4;
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offset = (pin % 8) * 4;
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data = readl(addr);
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data &= ~(0x7 << offset);
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data |= IO_INPUT << offset;
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writel(data, addr);
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dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr));
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}
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void gpio_direction_output(enum gpio_port port, enum gpio_pin pin, int value)
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{
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volatile rt_uint32_t addr;
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rt_uint32_t offset;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_A <= port) && (port < GPIO_PORT_NUM));
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RT_ASSERT((GPIO_PIN_0 <= pin) && (pin < GPIO_PIN_NUM));
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gpio_set_value(port, pin, value);
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addr = GPIOn_CFG_ADDR(port) + (pin / 8) * 4;
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offset = (pin % 8) * 4;
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data = readl(addr);
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data &= ~(0x7 << offset);
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data |= IO_OUTPUT << offset;
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writel(data, addr);
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dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr));
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}
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/*********************************************************
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** IRQ
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*********************************************************/
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static void gpio_ack_irq(enum gpio_port port, enum gpio_pin pin)
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{
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rt_uint32_t addr;
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rt_uint32_t data;
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addr = GPIOn_INT_STA_ADDR(port);
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data = readl(addr);
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data |= 0x1 << pin;
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writel(data, addr);
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}
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void gpio_select_irq_clock(enum gpio_port port, enum gpio_irq_clock clock)
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{
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rt_uint32_t addr;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_C < port) && (port < GPIO_PORT_NUM));
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addr = GPIOn_INT_DEB_ADDR(port - GPIO_PORT_D);
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data = readl(addr);
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data &= ~0x01;
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data |= clock;
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writel(data, addr);
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dbg_log(DBG_LOG, "[line]:%d addr:%08x data:%08x\n", __LINE__, addr, *((rt_uint32_t *)addr));
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}
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void gpio_set_debounce(enum gpio_port port, enum gpio_direction_type prescaler)
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{
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rt_uint32_t addr;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_C < port) && (port < GPIO_PORT_NUM));
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addr = GPIOn_INT_DEB_ADDR(port - GPIO_PORT_D);
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data = readl(addr);
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data &= ~(0x07 << 4);
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data |= prescaler << 4;
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writel(data, addr);
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dbg_log(DBG_LOG, "[line]:%d addr:%08x data:%08x\n", __LINE__, addr, *((rt_uint32_t *)addr));
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}
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void gpio_irq_enable(enum gpio_port port, enum gpio_pin pin)
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{
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rt_uint32_t addr;
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rt_uint32_t offset;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_C < port) && (port < GPIO_PORT_NUM));
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RT_ASSERT((GPIO_PIN_0 <= pin) && (pin < GPIO_PIN_NUM));
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addr = GPIOn_INT_CTRL_ADDR(port - GPIO_PORT_D);
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offset = pin;
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data = readl(addr);
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data |= 0x1 << offset;
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writel(data, addr);
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gpio_select_irq_clock(port, GPIO_IRQ_HOSC_24MHZ);
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dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr));
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}
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void gpio_irq_disable(enum gpio_port port, enum gpio_pin pin)
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{
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rt_uint32_t addr;
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rt_uint32_t offset;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_C < port) && (port < GPIO_PORT_NUM));
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RT_ASSERT((GPIO_PIN_0 <= pin) && (pin < GPIO_PIN_NUM));
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gpio_ack_irq(port - GPIO_PORT_D, pin);
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addr = GPIOn_INT_CTRL_ADDR(port - GPIO_PORT_D);
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offset = pin;
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data = readl(addr);
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data &= ~(0x1 << offset);
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writel(data, addr);
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dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr));
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}
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void gpio_set_irq_type(enum gpio_port port, enum gpio_pin pin, enum gpio_irq_type irq_type)
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{
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rt_uint32_t addr;
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rt_uint32_t offset;
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rt_uint32_t data;
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RT_ASSERT((GPIO_PORT_C < port) && (port < GPIO_PORT_NUM));
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RT_ASSERT((GPIO_PIN_0 <= pin) && (pin < GPIO_PIN_NUM));
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addr = GPIOn_INT_CFG_ADDR(port - GPIO_PORT_D) + (pin / 8) * 4;
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offset = (pin % 8) * 4;
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data = readl(addr);
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data &= ~(0x7 << offset);
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data |= irq_type << offset;
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writel(data, addr);
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dbg_log(DBG_LOG, "[line]:%d offset:%d addr:%08x data:%08x\n", __LINE__, offset, addr, *((rt_uint32_t *)addr));
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}
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static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_PORT_NUM];
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void gpio_set_irq_callback(enum gpio_port port, enum gpio_pin pin, void (*irq_cb)(void *), void *irq_arg)
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{
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RT_ASSERT((GPIO_PORT_C < port) && (port < GPIO_PORT_NUM));
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RT_ASSERT((GPIO_PIN_0 <= pin) && (pin < GPIO_PIN_NUM));
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_g_gpio_irq_tbl[port].irq_cb[pin] = irq_cb;
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_g_gpio_irq_tbl[port].irq_arg[pin] = irq_arg;
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}
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void gpio_clear_irq_callback(enum gpio_port port, enum gpio_pin pin)
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{
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gpio_irq_disable(port, pin);
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_g_gpio_irq_tbl[port].irq_cb[pin] = RT_NULL;
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_g_gpio_irq_tbl[port].irq_arg[pin] = RT_NULL;
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}
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static void gpio_irq_handler(int irq, void *param)
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{
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struct gpio_irq_def *irq_def = (struct gpio_irq_def *)param;
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rt_uint32_t pend, enable;
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int port, pin;
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rt_uint32_t addr;
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pin = 0;
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port = irq - PIOD_INTERRUPT;
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addr = GPIOn_INT_STA_ADDR(port);
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pend = readl(addr);
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addr = GPIOn_INT_CTRL_ADDR(port);
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enable = readl(addr);
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pend &= enable;
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while (pend)
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{
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if ((pend & 0x1) && (irq_def->irq_cb[pin] != RT_NULL))
|
||
|
|
{
|
||
|
|
dbg_log(DBG_LOG, "do irq callback...\n", port, pin);
|
||
|
|
irq_def->irq_cb[pin](irq_def->irq_arg[pin]);
|
||
|
|
}
|
||
|
|
pin++;
|
||
|
|
pend = pend >> 1;
|
||
|
|
gpio_ack_irq(port, pin);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#ifdef RT_USING_PIN
|
||
|
|
#include <rtdevice.h>
|
||
|
|
|
||
|
|
#define PIN_MAGIC (0x5A)
|
||
|
|
#define PIN_NUM(_N) (sizeof(_N) / sizeof(_N[0]))
|
||
|
|
|
||
|
|
struct _pin_index
|
||
|
|
{
|
||
|
|
rt_uint8_t id;
|
||
|
|
rt_uint8_t pin_port;
|
||
|
|
rt_uint8_t pin;
|
||
|
|
rt_uint8_t magic;
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct _pin_index pin_index[] =
|
||
|
|
{
|
||
|
|
{0, 0, 0, 0},
|
||
|
|
{1, 0, 0, 0},
|
||
|
|
{2, 0, 0, 0},
|
||
|
|
{3, 0, 0, 0},
|
||
|
|
{4, 0, 0, 0},
|
||
|
|
{5, 0, 0, 0},
|
||
|
|
{6, GPIO_PORT_D, GPIO_PIN_0, PIN_MAGIC},
|
||
|
|
{7, GPIO_PORT_D, GPIO_PIN_1, PIN_MAGIC},
|
||
|
|
{8, GPIO_PORT_D, GPIO_PIN_2, PIN_MAGIC},
|
||
|
|
{9, GPIO_PORT_D, GPIO_PIN_3, PIN_MAGIC},
|
||
|
|
{10, GPIO_PORT_D, GPIO_PIN_4, PIN_MAGIC},
|
||
|
|
{11, GPIO_PORT_D, GPIO_PIN_5, PIN_MAGIC},
|
||
|
|
{12, GPIO_PORT_D, GPIO_PIN_6, PIN_MAGIC},
|
||
|
|
{13, GPIO_PORT_D, GPIO_PIN_7, PIN_MAGIC},
|
||
|
|
{14, GPIO_PORT_D, GPIO_PIN_8, PIN_MAGIC},
|
||
|
|
{15, GPIO_PORT_D, GPIO_PIN_9, PIN_MAGIC},
|
||
|
|
{16, GPIO_PORT_D, GPIO_PIN_10, PIN_MAGIC},
|
||
|
|
{17, GPIO_PORT_D, GPIO_PIN_11, PIN_MAGIC},
|
||
|
|
{18, GPIO_PORT_D, GPIO_PIN_12, PIN_MAGIC},
|
||
|
|
{19, GPIO_PORT_D, GPIO_PIN_13, PIN_MAGIC},
|
||
|
|
{20, 0, 0, 0},
|
||
|
|
{21, GPIO_PORT_D, GPIO_PIN_14, PIN_MAGIC},
|
||
|
|
{22, 0, 0, 0},
|
||
|
|
{23, GPIO_PORT_D, GPIO_PIN_15, PIN_MAGIC},
|
||
|
|
{24, GPIO_PORT_D, GPIO_PIN_16, PIN_MAGIC},
|
||
|
|
{25, GPIO_PORT_D, GPIO_PIN_17, PIN_MAGIC},
|
||
|
|
{26, GPIO_PORT_D, GPIO_PIN_18, PIN_MAGIC},
|
||
|
|
{27, GPIO_PORT_D, GPIO_PIN_19, PIN_MAGIC},
|
||
|
|
{28, GPIO_PORT_D, GPIO_PIN_20, PIN_MAGIC},
|
||
|
|
{29, GPIO_PORT_D, GPIO_PIN_21, PIN_MAGIC},
|
||
|
|
{30, 0, 0, 0},
|
||
|
|
{31, 0, 0, 0},
|
||
|
|
{32, 0, 0, 0},
|
||
|
|
{33, 0, 0, 0},
|
||
|
|
{34, 0, 0, 0},
|
||
|
|
{35, 0, 0, 0},
|
||
|
|
{36, 0, 0, 0},
|
||
|
|
{37, GPIO_PORT_E, GPIO_PIN_12, PIN_MAGIC},
|
||
|
|
{38, GPIO_PORT_E, GPIO_PIN_11, PIN_MAGIC},
|
||
|
|
{39, GPIO_PORT_E, GPIO_PIN_10, PIN_MAGIC},
|
||
|
|
{40, GPIO_PORT_E, GPIO_PIN_9, PIN_MAGIC},
|
||
|
|
{41, GPIO_PORT_E, GPIO_PIN_8, PIN_MAGIC},
|
||
|
|
{42, GPIO_PORT_E, GPIO_PIN_7, PIN_MAGIC},
|
||
|
|
{43, GPIO_PORT_E, GPIO_PIN_6, PIN_MAGIC},
|
||
|
|
{44, GPIO_PORT_E, GPIO_PIN_5, PIN_MAGIC},
|
||
|
|
{45, GPIO_PORT_E, GPIO_PIN_4, PIN_MAGIC},
|
||
|
|
{46, GPIO_PORT_E, GPIO_PIN_3, PIN_MAGIC},
|
||
|
|
{47, GPIO_PORT_E, GPIO_PIN_2, PIN_MAGIC},
|
||
|
|
{48, GPIO_PORT_E, GPIO_PIN_1, PIN_MAGIC},
|
||
|
|
{49, GPIO_PORT_E, GPIO_PIN_0, PIN_MAGIC},
|
||
|
|
{50, 0, 0, 0},
|
||
|
|
{51, 0, 0, 0},
|
||
|
|
{52, 0, 0, 0},
|
||
|
|
{53, GPIO_PORT_F, GPIO_PIN_5, PIN_MAGIC},
|
||
|
|
{54, GPIO_PORT_F, GPIO_PIN_4, PIN_MAGIC},
|
||
|
|
{55, GPIO_PORT_F, GPIO_PIN_3, PIN_MAGIC},
|
||
|
|
{56, GPIO_PORT_F, GPIO_PIN_2, PIN_MAGIC},
|
||
|
|
{57, GPIO_PORT_F, GPIO_PIN_1, PIN_MAGIC},
|
||
|
|
{58, GPIO_PORT_F, GPIO_PIN_0, PIN_MAGIC},
|
||
|
|
{59, GPIO_PORT_C, GPIO_PIN_0, PIN_MAGIC},
|
||
|
|
{60, GPIO_PORT_C, GPIO_PIN_1, PIN_MAGIC},
|
||
|
|
{61, GPIO_PORT_C, GPIO_PIN_2, PIN_MAGIC},
|
||
|
|
{62, GPIO_PORT_C, GPIO_PIN_3, PIN_MAGIC},
|
||
|
|
{63, GPIO_PORT_A, GPIO_PIN_3, PIN_MAGIC},
|
||
|
|
{64, GPIO_PORT_A, GPIO_PIN_2, PIN_MAGIC},
|
||
|
|
{65, GPIO_PORT_A, GPIO_PIN_1, PIN_MAGIC},
|
||
|
|
{66, GPIO_PORT_A, GPIO_PIN_0, PIN_MAGIC},
|
||
|
|
};
|
||
|
|
|
||
|
|
static void pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpio_set_func(pin_index[pin].pin_port, pin_index[pin].pin, mode);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpio_set_value(pin_index[pin].pin_port, pin_index[pin].pin, value);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int pin_read(struct rt_device *device, rt_base_t pin)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
return gpio_get_value(pin_index[pin].pin_port, pin_index[pin].pin);
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin);
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpio_set_irq_callback(pin_index[pin].pin_port, pin_index[pin].pin, hdr, args);
|
||
|
|
gpio_set_irq_type(pin_index[pin].pin_port, pin_index[pin].pin, mode);
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
static rt_err_t pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin);
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
gpio_clear_irq_callback(pin_index[pin].pin_port, pin_index[pin].pin);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_err_t pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
|
||
|
|
{
|
||
|
|
if ((pin > PIN_NUM(pin_index)) || (pin_index[pin].magic != PIN_MAGIC))
|
||
|
|
{
|
||
|
|
dbg_log(DBG_ERROR, "pin:%d value wrongful\n", pin);
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (enabled)
|
||
|
|
gpio_irq_enable(pin_index[pin].pin_port, pin_index[pin].pin);
|
||
|
|
else
|
||
|
|
gpio_irq_disable(pin_index[pin].pin_port, pin_index[pin].pin);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
ID GPIO ID GPIO ID GPIO ID GPIO ID GPIO ID GPIO ID GPIO
|
||
|
|
6 PD0 13 PD7 21 PD14 29 PD21 43 PE6 53 PF5 60 PC1
|
||
|
|
7 PD1 14 PD8 23 PD15 37 PE12 44 PE5 54 PF4 61 PC2
|
||
|
|
8 PD2 15 PD9 24 PD16 38 PE11 45 PE4 55 PF3 62 PC3
|
||
|
|
9 PD3 16 PD10 25 PD17 39 PE10 46 PE3 56 PF2 63 PA3
|
||
|
|
10 PD4 17 PD11 26 PD18 40 PE9 47 PE2 57 PF1 64 PA2
|
||
|
|
11 PD5 18 PD12 27 PD19 41 PE8 48 PE1 58 PF0 65 PA1
|
||
|
|
12 PD6 19 PD13 28 PD20 42 PE7 49 PE0 59 PC0 66 PA0
|
||
|
|
*/
|
||
|
|
|
||
|
|
static const struct rt_pin_ops ops =
|
||
|
|
{
|
||
|
|
pin_mode,
|
||
|
|
pin_write,
|
||
|
|
pin_read,
|
||
|
|
pin_attach_irq,
|
||
|
|
pin_dettach_irq,
|
||
|
|
pin_irq_enable,
|
||
|
|
};
|
||
|
|
#endif
|
||
|
|
|
||
|
|
int rt_hw_gpio_init(void)
|
||
|
|
{
|
||
|
|
#ifdef RT_USING_PIN
|
||
|
|
rt_device_pin_register("gpio", &ops, RT_NULL);
|
||
|
|
#endif
|
||
|
|
/* install ISR */
|
||
|
|
rt_hw_interrupt_install(PIOD_INTERRUPT, gpio_irq_handler, &_g_gpio_irq_tbl[GPIO_PORT_D], "gpiod_irq");
|
||
|
|
rt_hw_interrupt_umask(PIOD_INTERRUPT);
|
||
|
|
|
||
|
|
rt_hw_interrupt_install(PIOE_INTERRUPT, gpio_irq_handler, &_g_gpio_irq_tbl[GPIO_PORT_E], "gpioe_irq");
|
||
|
|
rt_hw_interrupt_umask(PIOE_INTERRUPT);
|
||
|
|
|
||
|
|
rt_hw_interrupt_install(PIOF_INTERRUPT, gpio_irq_handler, &_g_gpio_irq_tbl[GPIO_PORT_F], "gpiof_irq");
|
||
|
|
rt_hw_interrupt_umask(PIOF_INTERRUPT);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
INIT_DEVICE_EXPORT(rt_hw_gpio_init);
|