217 lines
13 KiB
C
217 lines
13 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_defaultisr.h
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//
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// TITLE: F2837xD Device Default Interrupt Service Routines Definitions
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//
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//###########################################################################
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// $TI Release: F2837xD Support Library v3.05.00.00 $
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// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
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// $Copyright:
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// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef F2837xD_DEFAULT_ISR_H
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#define F2837xD_DEFAULT_ISR_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//
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// Default Interrupt Service Routine Declarations:
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// The following function prototypes are for the
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// default ISR routines used with the default PIE vector table.
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// This default vector table is found in the F2837xD_pievect.h
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// file.
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//
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interrupt void TIMER1_ISR(void); // CPU Timer 1 Interrupt
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interrupt void TIMER2_ISR(void); // CPU Timer 2 Interrupt
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interrupt void DATALOG_ISR(void); // Datalogging Interrupt
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interrupt void RTOS_ISR(void); // RTOS Interrupt
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interrupt void EMU_ISR(void); // Emulation Interrupt
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interrupt void NMI_ISR(void); // Non-Maskable Interrupt
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interrupt void ILLEGAL_ISR(void); // Illegal Operation Trap
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interrupt void USER1_ISR(void); // User Defined Trap 1
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interrupt void USER2_ISR(void); // User Defined Trap 2
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interrupt void USER3_ISR(void); // User Defined Trap 3
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interrupt void USER4_ISR(void); // User Defined Trap 4
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interrupt void USER5_ISR(void); // User Defined Trap 5
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interrupt void USER6_ISR(void); // User Defined Trap 6
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interrupt void USER7_ISR(void); // User Defined Trap 7
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interrupt void USER8_ISR(void); // User Defined Trap 8
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interrupt void USER9_ISR(void); // User Defined Trap 9
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interrupt void USER10_ISR(void); // User Defined Trap 10
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interrupt void USER11_ISR(void); // User Defined Trap 11
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interrupt void USER12_ISR(void); // User Defined Trap 12
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interrupt void ADCA1_ISR(void); // 1.1 - ADCA Interrupt 1
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interrupt void ADCB1_ISR(void); // 1.2 - ADCB Interrupt 1
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interrupt void ADCC1_ISR(void); // 1.3 - ADCC Interrupt 1
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interrupt void XINT1_ISR(void); // 1.4 - XINT1 Interrupt
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interrupt void XINT2_ISR(void); // 1.5 - XINT2 Interrupt
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interrupt void ADCD1_ISR(void); // 1.6 - ADCD Interrupt 1
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interrupt void TIMER0_ISR(void); // 1.7 - Timer 0 Interrupt
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interrupt void WAKE_ISR(void); // 1.8 - Standby and Halt Wakeup Interrupt
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interrupt void EPWM1_TZ_ISR(void); // 2.1 - ePWM1 Trip Zone Interrupt
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interrupt void EPWM2_TZ_ISR(void); // 2.2 - ePWM2 Trip Zone Interrupt
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interrupt void EPWM3_TZ_ISR(void); // 2.3 - ePWM3 Trip Zone Interrupt
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interrupt void EPWM4_TZ_ISR(void); // 2.4 - ePWM4 Trip Zone Interrupt
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interrupt void EPWM5_TZ_ISR(void); // 2.5 - ePWM5 Trip Zone Interrupt
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interrupt void EPWM6_TZ_ISR(void); // 2.6 - ePWM6 Trip Zone Interrupt
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interrupt void EPWM7_TZ_ISR(void); // 2.7 - ePWM7 Trip Zone Interrupt
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interrupt void EPWM8_TZ_ISR(void); // 2.8 - ePWM8 Trip Zone Interrupt
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interrupt void EPWM1_ISR(void); // 3.1 - ePWM1 Interrupt
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interrupt void EPWM2_ISR(void); // 3.2 - ePWM2 Interrupt
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interrupt void EPWM3_ISR(void); // 3.3 - ePWM3 Interrupt
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interrupt void EPWM4_ISR(void); // 3.4 - ePWM4 Interrupt
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interrupt void EPWM5_ISR(void); // 3.5 - ePWM5 Interrupt
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interrupt void EPWM6_ISR(void); // 3.6 - ePWM6 Interrupt
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interrupt void EPWM7_ISR(void); // 3.7 - ePWM7 Interrupt
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interrupt void EPWM8_ISR(void); // 3.8 - ePWM8 Interrupt
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interrupt void ECAP1_ISR(void); // 4.1 - eCAP1 Interrupt
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interrupt void ECAP2_ISR(void); // 4.2 - eCAP2 Interrupt
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interrupt void ECAP3_ISR(void); // 4.3 - eCAP3 Interrupt
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interrupt void ECAP4_ISR(void); // 4.4 - eCAP4 Interrupt
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interrupt void ECAP5_ISR(void); // 4.5 - eCAP5 Interrupt
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interrupt void ECAP6_ISR(void); // 4.6 - eCAP6 Interrupt
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interrupt void EQEP1_ISR(void); // 5.1 - eQEP1 Interrupt
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interrupt void EQEP2_ISR(void); // 5.2 - eQEP2 Interrupt
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interrupt void EQEP3_ISR(void); // 5.3 - eQEP3 Interrupt
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interrupt void SPIA_RX_ISR(void); // 6.1 - SPIA Receive Interrupt
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interrupt void SPIA_TX_ISR(void); // 6.2 - SPIA Transmit Interrupt
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interrupt void SPIB_RX_ISR(void); // 6.3 - SPIB Receive Interrupt
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interrupt void SPIB_TX_ISR(void); // 6.4 - SPIB Transmit Interrupt
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interrupt void MCBSPA_RX_ISR(void); // 6.5 - McBSPA Receive Interrupt
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interrupt void MCBSPA_TX_ISR(void); // 6.6 - McBSPA Transmit Interrupt
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interrupt void MCBSPB_RX_ISR(void); // 6.7 - McBSPB Receive Interrupt
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interrupt void MCBSPB_TX_ISR(void); // 6.8 - McBSPB Transmit Interrupt
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interrupt void DMA_CH1_ISR(void); // 7.1 - DMA Channel 1 Interrupt
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interrupt void DMA_CH2_ISR(void); // 7.2 - DMA Channel 2 Interrupt
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interrupt void DMA_CH3_ISR(void); // 7.3 - DMA Channel 3 Interrupt
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interrupt void DMA_CH4_ISR(void); // 7.4 - DMA Channel 4 Interrupt
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interrupt void DMA_CH5_ISR(void); // 7.5 - DMA Channel 5 Interrupt
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interrupt void DMA_CH6_ISR(void); // 7.6 - DMA Channel 6 Interrupt
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interrupt void I2CA_ISR(void); // 8.1 - I2CA Interrupt 1
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interrupt void I2CA_FIFO_ISR(void); // 8.2 - I2CA Interrupt 2
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interrupt void I2CB_ISR(void); // 8.3 - I2CB Interrupt 1
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interrupt void I2CB_FIFO_ISR(void); // 8.4 - I2CB Interrupt 2
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interrupt void SCIC_RX_ISR(void); // 8.5 - SCIC Receive Interrupt
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interrupt void SCIC_TX_ISR(void); // 8.6 - SCIC Transmit Interrupt
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interrupt void SCID_RX_ISR(void); // 8.7 - SCID Receive Interrupt
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interrupt void SCID_TX_ISR(void); // 8.8 - SCID Transmit Interrupt
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interrupt void SCIA_RX_ISR(void); // 9.1 - SCIA Receive Interrupt
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interrupt void SCIA_TX_ISR(void); // 9.2 - SCIA Transmit Interrupt
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interrupt void SCIB_RX_ISR(void); // 9.3 - SCIB Receive Interrupt
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interrupt void SCIB_TX_ISR(void); // 9.4 - SCIB Transmit Interrupt
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interrupt void CANA0_ISR(void); // 9.5 - CANA Interrupt 0
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interrupt void CANA1_ISR(void); // 9.6 - CANA Interrupt 1
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interrupt void CANB0_ISR(void); // 9.7 - CANB Interrupt 0
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interrupt void CANB1_ISR(void); // 9.8 - CANB Interrupt 1
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interrupt void ADCA_EVT_ISR(void); // 10.1 - ADCA Event Interrupt
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interrupt void ADCA2_ISR(void); // 10.2 - ADCA Interrupt 2
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interrupt void ADCA3_ISR(void); // 10.3 - ADCA Interrupt 3
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interrupt void ADCA4_ISR(void); // 10.4 - ADCA Interrupt 4
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interrupt void ADCB_EVT_ISR(void); // 10.5 - ADCB Event Interrupt
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interrupt void ADCB2_ISR(void); // 10.6 - ADCB Interrupt 2
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interrupt void ADCB3_ISR(void); // 10.7 - ADCB Interrupt 3
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interrupt void ADCB4_ISR(void); // 10.8 - ADCB Interrupt 4
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interrupt void CLA1_1_ISR(void); // 11.1 - CLA1 Interrupt 1
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interrupt void CLA1_2_ISR(void); // 11.2 - CLA1 Interrupt 2
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interrupt void CLA1_3_ISR(void); // 11.3 - CLA1 Interrupt 3
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interrupt void CLA1_4_ISR(void); // 11.4 - CLA1 Interrupt 4
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interrupt void CLA1_5_ISR(void); // 11.5 - CLA1 Interrupt 5
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interrupt void CLA1_6_ISR(void); // 11.6 - CLA1 Interrupt 6
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interrupt void CLA1_7_ISR(void); // 11.7 - CLA1 Interrupt 7
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interrupt void CLA1_8_ISR(void); // 11.8 - CLA1 Interrupt 8
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interrupt void XINT3_ISR(void); // 12.1 - XINT3 Interrupt
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interrupt void XINT4_ISR(void); // 12.2 - XINT4 Interrupt
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interrupt void XINT5_ISR(void); // 12.3 - XINT5 Interrupt
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interrupt void VCU_ISR(void); // 12.6 - VCU Interrupt
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interrupt void FPU_OVERFLOW_ISR(void); // 12.7 - FPU Overflow Interrupt
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interrupt void FPU_UNDERFLOW_ISR(void); // 12.8 - FPU Underflow Interrupt
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interrupt void IPC0_ISR(void); // 1.13 - IPC Interrupt 0
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interrupt void IPC1_ISR(void); // 1.14 - IPC Interrupt 1
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interrupt void IPC2_ISR(void); // 1.15 - IPC Interrupt 2
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interrupt void IPC3_ISR(void); // 1.16 - IPC Interrupt 3
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interrupt void EPWM9_TZ_ISR(void); // 2.9 - ePWM9 Trip Zone Interrupt
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interrupt void EPWM10_TZ_ISR(void); // 2.10 - ePWM10 Trip Zone Interrupt
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interrupt void EPWM11_TZ_ISR(void); // 2.11 - ePWM11 Trip Zone Interrupt
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interrupt void EPWM12_TZ_ISR(void); // 2.12 - ePWM12 Trip Zone Interrupt
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interrupt void EPWM9_ISR(void); // 3.9 - ePWM9 Interrupt
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interrupt void EPWM10_ISR(void); // 3.10 - ePWM10 Interrupt
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interrupt void EPWM11_ISR(void); // 3.11 - ePWM11 Interrupt
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interrupt void EPWM12_ISR(void); // 3.12 - ePWM12 Interrupt
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interrupt void SD1_ISR(void); // 5.9 - SD1 Interrupt
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interrupt void SD2_ISR(void); // 5.10 - SD2 Interrupt
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interrupt void SPIC_RX_ISR(void); // 6.9 - SPIC Receive Interrupt
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interrupt void SPIC_TX_ISR(void); // 6.10 - SPIC Transmit Interrupt
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interrupt void UPPA_ISR(void); // 8.15 - uPPA Interrupt
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interrupt void USBA_ISR(void); // 9.15 - USBA Interrupt
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interrupt void ADCC_EVT_ISR(void); // 10.9 - ADCC Event Interrupt
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interrupt void ADCC2_ISR(void); // 10.10 - ADCC Interrupt 2
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interrupt void ADCC3_ISR(void); // 10.11 - ADCC Interrupt 3
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interrupt void ADCC4_ISR(void); // 10.12 - ADCC Interrupt 4
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interrupt void ADCD_EVT_ISR(void); // 10.13 - ADCD Event Interrupt
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interrupt void ADCD2_ISR(void); // 10.14 - ADCD Interrupt 2
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interrupt void ADCD3_ISR(void); // 10.15 - ADCD Interrupt 3
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interrupt void ADCD4_ISR(void); // 10.16 - ADCD Interrupt 4
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interrupt void EMIF_ERROR_ISR(void); // 12.9 - EMIF Error Interrupt
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interrupt void RAM_CORRECTABLE_ERROR_ISR(void); // 12.10 - RAM Correctable
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// Error Interrupt
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interrupt void FLASH_CORRECTABLE_ERROR_ISR(void); // 12.11 - Flash Correctable
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// Error Interrupt
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interrupt void RAM_ACCESS_VIOLATION_ISR(void); // 12.12 - RAM Access
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// Violation Interrupt
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interrupt void SYS_PLL_SLIP_ISR(void); // 12.13 - System PLL Slip
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// Interrupt
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interrupt void AUX_PLL_SLIP_ISR(void); // 12.14 - Auxiliary PLL
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// Slip Interrupt
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interrupt void CLA_OVERFLOW_ISR(void); // 12.15 - CLA Overflow
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// Interrupt
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interrupt void CLA_UNDERFLOW_ISR(void); // 12.16 - CLA Underflow
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// Interrupt
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//
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// Catch-all for PIE Reserved Locations for testing purposes:
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//
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interrupt void PIE_RESERVED_ISR(void); // Reserved ISR
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interrupt void EMPTY_ISR(void); // Only does a return
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interrupt void NOTUSED_ISR(void); // Unused ISR
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of F2837xD_PIEVECT_H definition
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//
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// End of file
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//
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