394 lines
11 KiB
C
394 lines
11 KiB
C
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Email: opensource_embedded@phytium.com.cn
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*
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* Change Logs:
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* Date Author Notes
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* 2023/7/24 liqiaozhong first add, support intr
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*
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "interrupt.h"
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#include "rtdbg.h"
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#ifdef RT_USING_SMART
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#include "ioremap.h"
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#endif
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#include <string.h>
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#if defined(TARGET_E2000)
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#include "fparameters.h"
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#endif
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#include "fkernel.h"
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#include "fpinctrl.h"
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#include "fcpu_info.h"
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#include "ftypes.h"
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#include "board.h"
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#ifdef RT_USING_PIN
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#include "fiopad.h"
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#include "fgpio.h"
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#include "drv_gpio.h"
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/**************************** Type Definitions *******************************/
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typedef void (*FGpioOpsIrqHandler)(s32 vector, void *param);
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typedef struct
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{
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FGpioDirection direction;
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boolean en_irq;
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FGpioIrqType irq_type;
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FGpioOpsIrqHandler irq_handler;
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void *irq_args;
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} FGpioOpsPinConfig;
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typedef struct
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{
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FGpio ctrl;
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FGpioPin pins[FGPIO_PORT_NUM][FGPIO_PIN_NUM];
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FGpioOpsPinConfig pin_config[FGPIO_PORT_NUM][FGPIO_PIN_NUM];
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boolean init_ok;
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} FGpioOps;
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/***************** Macros (Inline Functions) Definitions *********************/
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#if defined(TARGET_E2000)
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#define FGPIO_VERSION_2
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#endif
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/************************** Variable Definitions *****************************/
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static FGpioOps gpio[FGPIO_NUM];
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extern FIOPadCtrl iopad_ctrl;
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/*******************************Api Functions*********************************/
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static void FGpioOpsSetupCtrlIRQ(FGpio *ctrl)
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{
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u32 cpu_id;
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u32 irq_num = ctrl->config.irq_num[0];
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GetCpuId(&cpu_id);
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LOG_D("In FGpioOpsSetupCtrlIRQ() -> cpu_id %d, irq_num %d\r\n", cpu_id, irq_num);
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rt_hw_interrupt_set_target_cpus(irq_num, cpu_id);
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rt_hw_interrupt_set_priority(irq_num, ctrl->config.irq_priority); /* setup interrupt */
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rt_hw_interrupt_install(irq_num, FGpioInterruptHandler, ctrl, NULL); /* register intr handler */
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rt_hw_interrupt_umask(irq_num);
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return;
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}
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/* setup gpio pin interrupt */
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static void FGpioOpsSetupPinIRQ(FGpio *ctrl, FGpioPin *const pin, FGpioOpsPinConfig *config)
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{
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u32 cpu_id;
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u32 irq_num = ctrl->config.irq_num[pin->index.pin];
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GetCpuId(&cpu_id);
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LOG_D("in FGpioOpsSetupPinIRQ() -> cpu_id %d, irq_num %d", cpu_id, irq_num);
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rt_hw_interrupt_set_target_cpus(irq_num, cpu_id);
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rt_hw_interrupt_set_priority(irq_num, ctrl->config.irq_priority); /* setup interrupt */
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rt_hw_interrupt_install(irq_num, FGpioInterruptHandler, config->irq_args, NULL); /* register intr handler */
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rt_hw_interrupt_umask(irq_num);
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return;
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}
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void FIOPadSetGpioMux(u32 ctrl_id_p, u32 pin_id_p)
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{
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#if defined(TARGET_E2000D)
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if (ctrl_id_p == FGPIO4_ID)
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{
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switch (pin_id_p)
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{
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case 11: /* gpio 4-a-11 */
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FIOPadSetFunc(&iopad_ctrl, FIOPAD_AC45_REG0_OFFSET, FIOPAD_FUNC6);
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break;
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case 12: /* gpio 4-a-12 */
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FIOPadSetFunc(&iopad_ctrl, FIOPAD_AE43_REG0_OFFSET, FIOPAD_FUNC6);
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break;
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default:
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LOG_E("Unsupported ctrl pin.");
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RT_ASSERT(0);
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break;
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}
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}
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else
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{
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LOG_E("Unsupported ctrl.");
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RT_ASSERT(0);
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}
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#endif
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#if defined(TARGET_E2000Q)
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if (ctrl_id_p == FGPIO4_ID)
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{
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switch (pin_id_p)
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{
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case 11: /* gpio 4-a-11 */
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FIOPadSetFunc(&iopad_ctrl, FIOPAD_AC49_REG0_OFFSET, FIOPAD_FUNC6);
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break;
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case 12: /* gpio 4-a-12 */
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FIOPadSetFunc(&iopad_ctrl, FIOPAD_AE47_REG0_OFFSET, FIOPAD_FUNC6);
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break;
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default:
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LOG_E("Unsupported ctrl pin.");
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RT_ASSERT(0);
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break;
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}
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}
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else
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{
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LOG_E("Unsupported ctrl.");
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RT_ASSERT(0);
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}
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#endif
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}
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/* on E2000, if u want use GPIO-4-11, set pin = FGPIO_OPS_PIN_INDEX(4, 0, 11) */
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static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
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{
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u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
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u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
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u32 pin_id = FGPIO_OPS_PIN_ID(pin);
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FGpioPinId gpio_pin_id;
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FError err = FGPIO_SUCCESS;
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FGpio *instance = &gpio[ctrl_id].ctrl;
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FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
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FGpioOpsPinConfig *pin_config = &gpio[ctrl_id].pin_config[port_id][pin_id];
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if (ctrl_id >= FGPIO_NUM)
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{
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LOG_E("ctrl_id too large!!!");
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return;
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}
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if (FALSE == gpio[ctrl_id].init_ok) /* init ctrl if needed */
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{
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FGpioConfig input_cfg = *FGpioLookupConfig(ctrl_id);
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memset(instance, 0, sizeof(*instance));
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#ifdef RT_USING_SMART
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input_cfg.base_addr = (uintptr)rt_ioremap((void *)input_cfg.base_addr, 0x1000);
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#endif
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err = FGpioCfgInitialize(instance, &input_cfg);
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if (FGPIO_SUCCESS != err)
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{
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LOG_E("Ctrl: %d init fail!!!\n", ctrl_id);
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return;
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}
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gpio[ctrl_id].init_ok = TRUE;
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}
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FIOPadSetGpioMux(ctrl_id, pin_id);
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if (FT_COMPONENT_IS_READY == pin_instance->is_ready)
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{
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FGpioPinDeInitialize(pin_instance);
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}
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gpio_pin_id.ctrl = ctrl_id;
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gpio_pin_id.port = port_id;
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gpio_pin_id.pin = pin_id;
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err = FGpioPinInitialize(instance, pin_instance, gpio_pin_id);
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if (FGPIO_SUCCESS != err)
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{
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LOG_E("Pin %d-%c-%d init fail!!!\n",
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ctrl_id,
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port_id == 0 ? 'a' : 'b',
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pin_id);
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return;
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}
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switch (mode)
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{
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case PIN_MODE_OUTPUT:
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pin_config->direction = FGPIO_DIR_OUTPUT;
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pin_config->en_irq = FALSE;
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break;
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case PIN_MODE_INPUT:
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pin_config->direction = FGPIO_DIR_INPUT;
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pin_config->en_irq = TRUE;
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pin_config->irq_type = FGPIO_IRQ_TYPE_EDGE_RISING;
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break;
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default:
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rt_kprintf("Not support mode %d!!!\n", mode);
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break;
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}
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FGpioSetDirection(pin_instance, pin_config->direction);
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rt_kprintf("Init GPIO-%d-%c-%d as an %sput pin\r\n",
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ctrl_id,
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port_id,
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pin_id, pin_config->direction == FGPIO_DIR_OUTPUT ? "out" : "in");
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}
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void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
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{
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u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
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u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
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u32 pin_id = FGPIO_OPS_PIN_ID(pin);
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FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
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if (pin_instance == RT_NULL)
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{
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rt_kprintf("Pin %d-%c-%d not set mode\n",
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ctrl_id,
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port_id == 0 ? 'a' : 'b',
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pin_id);
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return;
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}
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FGpioSetOutputValue(pin_instance, (value == PIN_HIGH) ? FGPIO_PIN_HIGH : FGPIO_PIN_LOW);
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}
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rt_int8_t drv_pin_read(struct rt_device *device, rt_base_t pin)
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{
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u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
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u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
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u32 pin_id = FGPIO_OPS_PIN_ID(pin);
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FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
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if (pin_instance == RT_NULL)
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{
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rt_kprintf("Pin %d-%c-%d not set mode\n",
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ctrl_id,
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port_id == 0 ? 'a' : 'b',
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pin_id);
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return RT_ERROR;
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}
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return FGpioGetInputValue(pin_instance) == FGPIO_PIN_HIGH ? PIN_HIGH : PIN_LOW;
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}
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rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_base_t pin,
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rt_uint8_t mode, void (*hdr)(void *args), void *args)
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{
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u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
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u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
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u32 pin_id = FGPIO_OPS_PIN_ID(pin);
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rt_base_t level;
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FGpio *instance = &gpio[ctrl_id].ctrl;
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FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
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FGpioOpsPinConfig *pin_config = &gpio[ctrl_id].pin_config[port_id][pin_id];
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level = rt_hw_interrupt_disable();
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pin_config->irq_handler = (FGpioOpsIrqHandler)hdr;
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pin_config->irq_args = args;
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if (pin_instance == RT_NULL)
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{
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LOG_E("GPIO%d-%c-%d not init yet.\n", ctrl_id, port_id == 0 ? 'a' : 'b', pin_id);
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return RT_ERROR;
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}
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if (pin_config->en_irq)
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{
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FGpioSetInterruptMask(pin_instance, FALSE);
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FGpioPinId pin_of_ctrl =
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{
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.ctrl = ctrl_id,
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.port = FGPIO_PORT_A,
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.pin = FGPIO_PIN_0
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};
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if (FGPIO_IRQ_BY_CONTROLLER == FGpioGetPinIrqSourceType(pin_of_ctrl)) /* setup for ctrl report interrupt */
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{
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FGpioOpsSetupCtrlIRQ(instance);
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LOG_I("GPIO-%d report irq by controller", ctrl_id);
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}
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else if (FGPIO_IRQ_BY_PIN == FGpioGetPinIrqSourceType(pin_of_ctrl))
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{
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FGpioOpsSetupPinIRQ(instance, pin_instance, pin_config);
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LOG_I("GPIO-%d report irq by pin", ctrl_id);
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}
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switch (mode)
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{
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case PIN_IRQ_MODE_RISING:
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pin_config->irq_type = FGPIO_IRQ_TYPE_EDGE_RISING;
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break;
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case PIN_IRQ_MODE_FALLING:
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pin_config->irq_type = FGPIO_IRQ_TYPE_EDGE_FALLING;
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break;
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case PIN_IRQ_MODE_LOW_LEVEL:
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pin_config->irq_type = FGPIO_IRQ_TYPE_LEVEL_LOW;
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break;
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case PIN_IRQ_MODE_HIGH_LEVEL:
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pin_config->irq_type = FGPIO_IRQ_TYPE_LEVEL_HIGH;
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break;
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default:
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LOG_E("Do not spport irq_mode: %d\n", mode);
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break;
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}
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FGpioSetInterruptType(pin_instance, pin_config->irq_type);
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FGpioRegisterInterruptCB(pin_instance, pin_config->irq_handler,
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pin_config->irq_args, TRUE); /* register intr callback */
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}
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_base_t pin)
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{
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u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
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u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
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u32 pin_id = FGPIO_OPS_PIN_ID(pin);
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rt_base_t level;
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FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
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FGpioOpsPinConfig *pin_config = &gpio[ctrl_id].pin_config[port_id][pin_id];
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if (pin_instance == RT_NULL)
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{
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rt_kprintf("pin %d-%c-%d not set mode\n",
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ctrl_id,
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port_id == 0 ? 'a' : 'b',
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pin_id);
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return RT_ERROR;
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}
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level = rt_hw_interrupt_disable();
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pin_config->irq_handler = RT_NULL;
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pin_config->irq_args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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|
|
rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
|
||
|
|
{
|
||
|
|
u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
|
||
|
|
u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
|
||
|
|
u32 pin_id = FGPIO_OPS_PIN_ID(pin);
|
||
|
|
FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
|
||
|
|
|
||
|
|
if (pin_instance == RT_NULL)
|
||
|
|
{
|
||
|
|
rt_kprintf("Pin %d-%c-%d not set mode\n",
|
||
|
|
ctrl_id,
|
||
|
|
port_id == 0 ? 'a' : 'b',
|
||
|
|
pin_id);
|
||
|
|
return RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
FGpioSetInterruptMask(pin_instance, enabled);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct rt_pin_ops drv_pin_ops =
|
||
|
|
{
|
||
|
|
.pin_mode = drv_pin_mode,
|
||
|
|
.pin_write = drv_pin_write,
|
||
|
|
.pin_read = drv_pin_read,
|
||
|
|
|
||
|
|
.pin_attach_irq = drv_pin_attach_irq,
|
||
|
|
.pin_detach_irq = drv_pin_detach_irq,
|
||
|
|
.pin_irq_enable = drv_pin_irq_enable,
|
||
|
|
.pin_get = RT_NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
int ft_pin_init(void)
|
||
|
|
{
|
||
|
|
rt_err_t ret = RT_EOK;
|
||
|
|
ret = rt_device_pin_register("pin", &drv_pin_ops, RT_NULL);
|
||
|
|
rt_kprintf("Register pin with return: %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
INIT_DEVICE_EXPORT(ft_pin_init);
|
||
|
|
#endif /* RT_USING_PIN */
|