2017-09-15 18:10:51 +08:00
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//*****************************************************************************
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//
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// am_hal_iom.h
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//! @file
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//!
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//! @brief Functions for accessing and configuring the IO Master module
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//!
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//! @addtogroup iom2 IO Master (SPI/I2C)
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//! @ingroup apollo2hal
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//! @{
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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2018-09-21 16:10:44 +08:00
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// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
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2017-09-15 18:10:51 +08:00
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//
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//*****************************************************************************
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#ifndef AM_HAL_IOM_H
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#define AM_HAL_IOM_H
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//*****************************************************************************
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//
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// Macro definitions
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! @name IOM Clock Frequencies
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//! @brief Macro definitions for common SPI and I2C clock frequencies.
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//!
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//! These macros may be used with the ui32ClockFrequency member of the
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//! am_hal_iom_config_t structure to set the clock frequency of the serial
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//! interfaces.
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//!
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//! This list of frequencies is not exhaustive by any means. If your desired
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//! frequency is not in this list, simply set ui32ClockFrequency to the
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//! desired frequency (in Hz) when calling am_hal_iom_config().
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//
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//*****************************************************************************
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#define AM_HAL_IOM_24MHZ 24000000
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#define AM_HAL_IOM_16MHZ 16000000
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#define AM_HAL_IOM_12MHZ 12000000
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#define AM_HAL_IOM_8MHZ 8000000
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#define AM_HAL_IOM_6MHZ 6000000
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#define AM_HAL_IOM_4MHZ 4000000
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#define AM_HAL_IOM_3MHZ 3000000
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#define AM_HAL_IOM_2MHZ 2000000
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#define AM_HAL_IOM_1_5MHZ 1500000
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#define AM_HAL_IOM_1MHZ 1000000
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2018-09-21 16:10:44 +08:00
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#define AM_HAL_IOM_800KHZ 800000
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#define AM_HAL_IOM_750KHZ 750000
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#define AM_HAL_IOM_500KHZ 500000
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#define AM_HAL_IOM_400KHZ 400000
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#define AM_HAL_IOM_375KHZ 375000
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#define AM_HAL_IOM_250KHZ 250000
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2018-09-21 16:10:44 +08:00
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#define AM_HAL_IOM_200KHZ 200000
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2017-09-15 18:10:51 +08:00
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#define AM_HAL_IOM_125KHZ 125000
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#define AM_HAL_IOM_100KHZ 100000
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#define AM_HAL_IOM_50KHZ 50000
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#define AM_HAL_IOM_10KHZ 10000
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// Hardware FIFO Size
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#define AM_HAL_IOM_MAX_FIFO_SIZE 128
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//*****************************************************************************
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//
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//! @name IOM Physical Protocols
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//! @brief Macro Definitions for general IOM configuration.
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//!
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//! These macros may be used with the am_hal_iom_config_t structure to set the
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//! operating parameters of each serial IO master module. Choose SPIMODE to
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//! select the SPI interface, or I2CMODE to select the I2C interface.
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_IOM_SPIMODE AM_REG_IOMSTR_CFG_IFCSEL(1)
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#define AM_HAL_IOM_I2CMODE AM_REG_IOMSTR_CFG_IFCSEL(0)
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//! @}
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//*****************************************************************************
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//
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//! @name IOM Operations
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//! @brief Macro definitions used for ui32Operation parameters.
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//!
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//! These macros may be used to specify which action an IOM command will
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//! execute. The 'OFFSET' operations will cause the IOM hardware to transmit the
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//! provided 1-byte 'offset' before executing the rest of the command.
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_IOM_WRITE 0x00000000
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#define AM_HAL_IOM_READ 0x80000000
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//! @}
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//*****************************************************************************
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//
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//! @name Command Options
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//! @brief Macro definitions used for ui32Options parameters.
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//!
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//! These macros are all related to SPI or I2C command words. They can be used
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//! to set specific options on a per-transaction basis.
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//!
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//! - CS_LOW - Do not raise the CS signal at the end of this SPI command.
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//! - NO_STOP - Do not release the I2C bus with a STOP bit after this command.
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//! - LSB_FIRST - Reverse the payload bits of this command.
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//! - 10BIT_ADDRESS - (I2C only) use a 10-bit I2C address protocol.
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//! - RAW - Don't use an offset byte.
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//! - OFFSET() - Send this 1-byte offset as the first byte of the transaction.
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//! This can be used to access "registers" in external I2C devices, or add a
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//! 1-byte write to the beginning of a SPI write or read command. See
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//! "normal mode" operation in the I2C/SPI Master section of the datasheet
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//! for more information on this parameter.
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_IOM_CS_LOW 0x10000000
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#define AM_HAL_IOM_NO_STOP 0x10000000
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#define AM_HAL_IOM_LSB_FIRST 0x08000000
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#define AM_HAL_IOM_10BIT_ADDRESS 0x04000000
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#define AM_HAL_IOM_RAW 0x40000000
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#define AM_HAL_IOM_OFFSET(n) (((n) << 8) & 0x0000FF00)
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//! @}
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//*****************************************************************************
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//
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//! @name IOM Interrupts
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//! @brief Macro definitions for IOM interrupt status bits.
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//!
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//! These macros correspond to the bits in the IOM interrupt status register.
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//! They may be used with any of the \e am_hal_iom_int_x() functions.
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//!
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//! @{
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//
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//*****************************************************************************
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#define AM_HAL_IOM_INT_ARB AM_REG_IOMSTR_INTEN_ARB_M
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#define AM_HAL_IOM_INT_STOP AM_REG_IOMSTR_INTEN_STOP_M
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#define AM_HAL_IOM_INT_START AM_REG_IOMSTR_INTEN_START_M
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#define AM_HAL_IOM_INT_ICMD AM_REG_IOMSTR_INTEN_ICMD_M
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#define AM_HAL_IOM_INT_IACC AM_REG_IOMSTR_INTEN_IACC_M
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#define AM_HAL_IOM_INT_WTLEN AM_REG_IOMSTR_INTEN_WTLEN_M
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#define AM_HAL_IOM_INT_NAK AM_REG_IOMSTR_INTEN_NAK_M
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#define AM_HAL_IOM_INT_FOVFL AM_REG_IOMSTR_INTEN_FOVFL_M
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#define AM_HAL_IOM_INT_FUNDFL AM_REG_IOMSTR_INTEN_FUNDFL_M
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#define AM_HAL_IOM_INT_THR AM_REG_IOMSTR_INTEN_THR_M
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#define AM_HAL_IOM_INT_CMDCMP AM_REG_IOMSTR_INTEN_CMDCMP_M
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2018-09-21 16:10:44 +08:00
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#define AM_HAL_IOM_INT_ALL ( \
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AM_HAL_IOM_INT_ARB | \
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AM_HAL_IOM_INT_STOP | \
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AM_HAL_IOM_INT_START | \
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AM_HAL_IOM_INT_ICMD | \
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AM_HAL_IOM_INT_IACC | \
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AM_HAL_IOM_INT_WTLEN | \
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AM_HAL_IOM_INT_NAK | \
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AM_HAL_IOM_INT_FOVFL | \
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AM_HAL_IOM_INT_FUNDFL | \
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AM_HAL_IOM_INT_THR | \
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AM_HAL_IOM_INT_CMDCMP)
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#define AM_HAL_IOM_INT_SWERR ( \
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AM_HAL_IOM_INT_ICMD | \
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AM_HAL_IOM_INT_FOVFL | \
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AM_HAL_IOM_INT_FUNDFL | \
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AM_HAL_IOM_INT_IACC)
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#define AM_HAL_IOM_INT_I2CARBERR ( \
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AM_HAL_IOM_INT_ARB | \
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AM_HAL_IOM_INT_START | \
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AM_HAL_IOM_INT_STOP)
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2017-09-15 18:10:51 +08:00
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//! @}
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//*****************************************************************************
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//
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2018-09-21 16:10:44 +08:00
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//! @name Software IOM modules
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//! @brief Macro definitions for using the software I2C interface.
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//!
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//! Use this macro as the module number for standard IOM functions to emulate
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//! them using the bit-banged i2c interface.
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2017-09-15 18:10:51 +08:00
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//!
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//! @{
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//
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//*****************************************************************************
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2018-09-21 16:10:44 +08:00
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#define AM_HAL_IOM_I2CBB_MODULE AM_REG_IOMSTR_NUM_MODULES
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//! @}
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//*****************************************************************************
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//
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2018-09-21 16:10:44 +08:00
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//! @name IOM Return Codes
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//! @brief Enum definitions for defining return values for IOM APIs
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//!
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2018-09-21 16:10:44 +08:00
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//! This enum defines possible values for non-void IOM APIs
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2017-09-15 18:10:51 +08:00
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//!
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//! @{
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//
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//*****************************************************************************
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2018-09-21 16:10:44 +08:00
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typedef enum
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{
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AM_HAL_IOM_SUCCESS = 0,
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AM_HAL_IOM_ERR_TIMEOUT,
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AM_HAL_IOM_ERR_INVALID_MODULE,
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AM_HAL_IOM_ERR_INVALID_PARAM,
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AM_HAL_IOM_ERR_INVALID_CFG,
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AM_HAL_IOM_ERR_INVALID_OPER,
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AM_HAL_IOM_ERR_I2C_NAK,
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AM_HAL_IOM_ERR_I2C_ARB,
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AM_HAL_IOM_ERR_RESOURCE_ERR,
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} am_hal_iom_status_e ;
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2017-09-15 18:10:51 +08:00
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//! @}
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//*****************************************************************************
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//
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//! @brief Union type for a word-aligned, byte-addressable array.
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//!
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//! This is a convenience macro that may be used to define byte-addressable
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//! arrays with 32-bit alignment. This allows the programmer to define SPI or
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//! I2C transactions as a series of 8-bit values, but also write them to the
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//! IOM FIFO efficiently as a series of 32-bit values.
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//!
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//! Example usage:
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//!
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//! @code
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//! //
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//! // Declare a buffer array with at least 3-bytes worth of space.
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//! //
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//! am_hal_iom_buffer(3) sBuffer;
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//!
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//! //
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//! // Populate the buffer with a 3-byte command.
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//! //
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//! sBuffer.bytes[0] = 's';
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//! sBuffer.bytes[1] = 'p';
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//! sBuffer.bytes[2] = 'i';
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//!
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//! //
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//! // Send the buffer over the spi interface.
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//! //
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//! am_hal_iom_spi_write(psDevice, sBuffer.words, 3, 0);
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//!
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//! @endcode
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//
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//*****************************************************************************
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#define am_hal_iom_buffer(A) \
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union \
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{ \
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uint32_t words[(A + 3) >> 2]; \
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uint8_t bytes[A]; \
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}
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//*****************************************************************************
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//
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//! @brief Configuration structure for the IO master module.
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//
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//*****************************************************************************
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typedef struct
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{
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//
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//! @brief Selects the physical protocol for the IO master module. Choose
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//! either AM_HAL_IOM_SPIMODE or AM_HAL_IOM_I2CMODE.
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//
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uint32_t ui32InterfaceMode;
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//
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//! @brief Selects the output clock frequency for SPI or I2C mode. Choose
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//! one of the AM_HAL_IOM_nMHZ or AM_HAL_IOM_nKHZ macros.
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//
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uint32_t ui32ClockFrequency;
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|
|
|
|
//
|
|
|
|
|
//! Select the SPI clock phase (unused in I2C mode).
|
|
|
|
|
//
|
|
|
|
|
bool bSPHA;
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
//! Select the SPI clock polarity (unused in I2C mode).
|
|
|
|
|
//
|
|
|
|
|
bool bSPOL;
|
2018-09-21 16:10:44 +08:00
|
|
|
|
2017-09-15 18:10:51 +08:00
|
|
|
//
|
|
|
|
|
//! @brief Select the FIFO write threshold.
|
|
|
|
|
//!
|
|
|
|
|
//! The IOM controller will generate a processor interrupt when the number
|
|
|
|
|
//! of entries in the FIFO goes *below* this number.
|
|
|
|
|
//
|
|
|
|
|
uint8_t ui8WriteThreshold;
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
//! @brief Select the FIFO read threshold.
|
|
|
|
|
//!
|
|
|
|
|
//! The IOM controller will generate a processor interrupt when the number
|
|
|
|
|
//! of entries in the FIFO grows *larger* than this number.
|
|
|
|
|
//
|
|
|
|
|
uint8_t ui8ReadThreshold;
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
am_hal_iom_config_t;
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
//! Configuration structure for an individual SPI device.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
typedef struct
|
|
|
|
|
{
|
|
|
|
|
//
|
|
|
|
|
//! IOM module to use for communicating with this device.
|
|
|
|
|
//
|
|
|
|
|
uint32_t ui32Module;
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
//! Chip select signal that should be used for this device.
|
|
|
|
|
//
|
|
|
|
|
uint32_t ui32ChipSelect;
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
//! Additional options that will ALWAYS be ORed into the command word.
|
|
|
|
|
//
|
|
|
|
|
uint32_t ui32Options;
|
|
|
|
|
}
|
|
|
|
|
am_hal_iom_spi_device_t;
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
//! Configuration structure for an individual I2C device.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
typedef struct
|
|
|
|
|
{
|
|
|
|
|
//
|
|
|
|
|
//! IOM module to use for communicating with this device.
|
|
|
|
|
//
|
|
|
|
|
uint32_t ui32Module;
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
//! I2C address associated with this device.
|
|
|
|
|
//
|
|
|
|
|
uint32_t ui32BusAddress;
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
//! Additional options that will ALWAYS be ORed into the command word.
|
|
|
|
|
//
|
|
|
|
|
uint32_t ui32Options;
|
|
|
|
|
}
|
|
|
|
|
am_hal_iom_i2c_device_t;
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Typedef for non-blocking function callbacks.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
typedef void (*am_hal_iom_callback_t)(void);
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Typedef for a function that waits until the IOM queue is empty.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
typedef void (*am_hal_iom_queue_flush_t)(uint32_t);
|
|
|
|
|
|
|
|
|
|
extern am_hal_iom_queue_flush_t am_hal_iom_queue_flush;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Operations
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
#define AM_HAL_IOM_QUEUE_SPI_WRITE 0
|
|
|
|
|
#define AM_HAL_IOM_QUEUE_SPI_READ 1
|
|
|
|
|
#define AM_HAL_IOM_QUEUE_I2C_WRITE 2
|
|
|
|
|
#define AM_HAL_IOM_QUEUE_I2C_READ 3
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Structure to hold IOM operations.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
typedef struct
|
|
|
|
|
{
|
|
|
|
|
uint32_t ui32Operation;
|
|
|
|
|
uint32_t ui32Module;
|
|
|
|
|
uint32_t ui32ChipSelect;
|
|
|
|
|
uint32_t *pui32Data;
|
|
|
|
|
uint32_t ui32NumBytes;
|
|
|
|
|
uint32_t ui32Options;
|
|
|
|
|
am_hal_iom_callback_t pfnCallback;
|
|
|
|
|
}
|
|
|
|
|
am_hal_iom_queue_entry_t;
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Structure to hold IOM configuration during module power-down.
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
typedef struct
|
|
|
|
|
{
|
|
|
|
|
uint32_t FIFOTHR;
|
|
|
|
|
uint32_t CLKCFG;
|
|
|
|
|
uint32_t CFG;
|
|
|
|
|
uint32_t INTEN;
|
|
|
|
|
uint32_t bValid;
|
|
|
|
|
}
|
|
|
|
|
am_hal_iom_pwrsave_t;
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Global variables
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
extern am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES];
|
2018-09-21 16:10:44 +08:00
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
extern "C"
|
|
|
|
|
{
|
|
|
|
|
#endif
|
2017-09-15 18:10:51 +08:00
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// External function definitions
|
|
|
|
|
//
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
extern void am_hal_iom_pwrctrl_enable(uint32_t ui32Module);
|
|
|
|
|
extern void am_hal_iom_pwrctrl_disable(uint32_t ui32Module);
|
|
|
|
|
extern void am_hal_iom_power_on_restore(uint32_t ui32Module);
|
|
|
|
|
extern void am_hal_iom_power_off_save(uint32_t ui32Module);
|
|
|
|
|
extern void am_hal_iom_config(uint32_t ui32Module,
|
|
|
|
|
const am_hal_iom_config_t *psConfig);
|
|
|
|
|
extern uint32_t am_hal_iom_frequency_get(uint32_t ui32Module);
|
|
|
|
|
extern void am_hal_iom_enable(uint32_t ui32Module);
|
|
|
|
|
extern void am_hal_iom_disable(uint32_t ui32Module);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t *pui32Data, uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t *pui32Data, uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_spi_fullduplex(uint32_t ui32Module, uint32_t ui32ChipSelect,
|
|
|
|
|
uint32_t *pui32TxData, uint32_t *pui32RxData,
|
|
|
|
|
uint32_t ui32NumBytes, uint32_t ui32Options);
|
|
|
|
|
|
|
|
|
|
extern am_hal_iom_status_e am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t *pui32Data, uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t *pui32Data, uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_spi_fullduplex_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
|
|
|
|
|
uint32_t *pui32TxData, uint32_t *pui32RxData,
|
|
|
|
|
uint32_t ui32NumBytes, uint32_t ui32Options);
|
|
|
|
|
extern am_hal_iom_status_e am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t *pui32Data, uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options,
|
|
|
|
|
am_hal_iom_callback_t pfnCallback);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t *pui32Data, uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options,
|
|
|
|
|
am_hal_iom_callback_t pfnCallback);
|
|
|
|
|
extern void am_hal_iom_spi_cmd_run(uint32_t ui32Operation,
|
|
|
|
|
uint32_t ui32Module,
|
|
|
|
|
uint32_t ui32ChipSelect,
|
|
|
|
|
uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_i2c_write(uint32_t ui32Module,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t ui32BusAddress,
|
|
|
|
|
uint32_t *pui32Data,
|
|
|
|
|
uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_i2c_read(uint32_t ui32Module,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t ui32BusAddress,
|
|
|
|
|
uint32_t *pui32Data,
|
|
|
|
|
uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_i2c_write_nq(uint32_t ui32Module,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t ui32BusAddress,
|
|
|
|
|
uint32_t *pui32Data,
|
|
|
|
|
uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_i2c_read_nq(uint32_t ui32Module,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t ui32BusAddress,
|
|
|
|
|
uint32_t *pui32Data,
|
|
|
|
|
uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_i2c_write_nb(uint32_t ui32Module,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t ui32BusAddress,
|
|
|
|
|
uint32_t *pui32Data,
|
|
|
|
|
uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options,
|
|
|
|
|
am_hal_iom_callback_t pfnCallback);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_i2c_read_nb(uint32_t ui32Module,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t ui32BusAddress,
|
|
|
|
|
uint32_t *pui32Data,
|
|
|
|
|
uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options,
|
|
|
|
|
am_hal_iom_callback_t pfnCallback);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_i2c_cmd_run(uint32_t ui32Operation,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t ui32Module,
|
|
|
|
|
uint32_t ui32BusAddress,
|
|
|
|
|
uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options);
|
|
|
|
|
extern void am_hal_iom_command_repeat_set(uint32_t ui32Module,
|
|
|
|
|
uint32_t ui32CmdCount);
|
|
|
|
|
extern uint32_t am_hal_iom_status_get(uint32_t ui32Module);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_error_status_get(uint32_t ui32Module);
|
2017-09-15 18:10:51 +08:00
|
|
|
extern uint32_t am_hal_iom_fifo_write(uint32_t ui32Module, uint32_t *pui32Data,
|
|
|
|
|
uint32_t ui32NumBytes);
|
|
|
|
|
extern uint32_t am_hal_iom_fifo_read(uint32_t ui32Module, uint32_t *pui32Data,
|
|
|
|
|
uint32_t ui32NumBytes);
|
|
|
|
|
extern uint8_t am_hal_iom_fifo_empty_slots(uint32_t ui32Module);
|
|
|
|
|
extern uint8_t am_hal_iom_fifo_full_slots(uint32_t ui32Module);
|
|
|
|
|
extern void am_hal_iom_poll_complete(uint32_t ui32Module);
|
|
|
|
|
extern void am_hal_iom_int_service(uint32_t ui32Module, uint32_t ui32Status);
|
|
|
|
|
extern void am_hal_iom_int_enable(uint32_t ui32Module, uint32_t ui32Interrupt);
|
|
|
|
|
extern uint32_t am_hal_iom_int_enable_get(uint32_t ui32Module);
|
|
|
|
|
extern void am_hal_iom_int_disable(uint32_t ui32Module, uint32_t ui32Interrupt);
|
|
|
|
|
extern void am_hal_iom_int_clear(uint32_t ui32Module, uint32_t ui32Interrupt);
|
|
|
|
|
extern void am_hal_iom_int_set(uint32_t ui32Module, uint32_t ui32Interrupt);
|
|
|
|
|
extern uint32_t am_hal_iom_int_status_get(uint32_t ui32Module, bool bEnabledOnly);
|
|
|
|
|
extern void am_hal_iom_queue_init(uint32_t ui32ModuleNum,
|
|
|
|
|
am_hal_iom_queue_entry_t *psQueueMemory,
|
|
|
|
|
uint32_t ui32QueueMemSize);
|
|
|
|
|
extern uint32_t am_hal_iom_queue_length_get(uint32_t ui32Module);
|
|
|
|
|
extern void am_hal_iom_sleeping_queue_flush(uint32_t ui32Module);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t *pui32Data, uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options,
|
|
|
|
|
am_hal_iom_callback_t pfnCallback);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t *pui32Data, uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options,
|
|
|
|
|
am_hal_iom_callback_t pfnCallback);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t *pui32Data, uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options,
|
|
|
|
|
am_hal_iom_callback_t pfnCallback);
|
2018-09-21 16:10:44 +08:00
|
|
|
extern am_hal_iom_status_e am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress,
|
2017-09-15 18:10:51 +08:00
|
|
|
uint32_t *pui32Data, uint32_t ui32NumBytes,
|
|
|
|
|
uint32_t ui32Options,
|
|
|
|
|
am_hal_iom_callback_t pfnCallback);
|
|
|
|
|
extern void am_hal_iom_queue_start_next_msg(uint32_t ui32Module);
|
|
|
|
|
extern void am_hal_iom_queue_service(uint32_t ui32Module, uint32_t ui32Status);
|
|
|
|
|
|
|
|
|
|
//*****************************************************************************
|
|
|
|
|
//
|
|
|
|
|
// Helper functions.
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//
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//*****************************************************************************
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#define AM_IOMASTER_ISR_QUEUE(x) \
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void am_iomaster##x##_isr(void) \
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{ \
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uint32_t ui32IntStatus; \
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ui32IntStatus = am_hal_iom_int_status_get(x, false); \
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am_hal_iom_int_clear(x, ui32IntStatus); \
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am_hal_iom_queue_service(x, ui32IntStatus); \
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}
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#define AM_IOMASTER_ISR_NB(x) \
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void am_iomaster##x##_isr(void) \
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{ \
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uint32_t ui32IntStatus; \
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ui32IntStatus = am_hal_iom_int_status_get(x, false); \
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am_hal_iom_int_clear(x, ui32IntStatus); \
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am_hal_iom_int_service(x, ui32IntStatus); \
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}
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2018-09-21 16:10:44 +08:00
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#ifdef __cplusplus
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}
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#endif
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2017-09-15 18:10:51 +08:00
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#endif // AM_HAL_IOM_H
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//*****************************************************************************
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//
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// End Doxygen group.
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//! @}
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//
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//*****************************************************************************
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