2022-10-20 09:40:14 +08:00
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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2022-07-13 19:56:14 +08:00
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*
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2022-10-20 09:40:14 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2022-07-13 19:56:14 +08:00
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*
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2022-10-20 09:40:14 +08:00
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* Change Logs:
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* Date Author Notes
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* 2022-10-19 Nations first version
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2022-07-13 19:56:14 +08:00
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*/
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#include "drv_adc.h"
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#ifdef RT_USING_ADC
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2022-10-20 09:40:14 +08:00
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#if defined(BSP_USING_ADC) || defined(BSP_USING_ADC1) || \
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defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) || \
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defined(BSP_USING_ADC4)
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2022-07-13 19:56:14 +08:00
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static struct n32_adc_config adc_config[] =
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{
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2022-10-20 09:40:14 +08:00
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#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
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#ifdef BSP_USING_ADC
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{
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"adc",
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ADC,
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},
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#endif
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#endif
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2022-07-13 19:56:14 +08:00
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#ifdef BSP_USING_ADC1
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{
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2022-10-20 09:40:14 +08:00
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"adc1",
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ADC1,
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2022-07-13 19:56:14 +08:00
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},
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#endif
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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#ifdef BSP_USING_ADC2
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{
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2022-10-20 09:40:14 +08:00
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"adc2",
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ADC2,
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2022-07-13 19:56:14 +08:00
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},
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#endif
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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#ifdef BSP_USING_ADC3
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{
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2022-10-20 09:40:14 +08:00
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"adc3",
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ADC3,
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2022-07-13 19:56:14 +08:00
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},
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#endif
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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#ifdef BSP_USING_ADC4
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{
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2022-10-20 09:40:14 +08:00
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"adc4",
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ADC4,
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2022-07-13 19:56:14 +08:00
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},
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#endif
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};
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static struct n32_adc adc_obj[sizeof(adc_config) / sizeof(adc_config[0])] = {0};
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static void n32_adc_init(struct n32_adc_config *config)
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{
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ADC_InitType ADC_InitStructure;
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2022-10-20 09:40:14 +08:00
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ADC_DeInit((ADC_Module*)config->adc_periph);
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/* ADC configuration */
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2023-01-05 14:45:17 +08:00
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#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
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2022-07-13 19:56:14 +08:00
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ADC_InitStructure.WorkMode = ADC_WORKMODE_INDEPENDENT;
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2022-10-20 09:40:14 +08:00
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#endif
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2022-07-13 19:56:14 +08:00
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ADC_InitStructure.MultiChEn = DISABLE;
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ADC_InitStructure.ContinueConvEn = DISABLE;
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ADC_InitStructure.ExtTrigSelect = ADC_EXT_TRIGCONV_NONE;
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ADC_InitStructure.DatAlign = ADC_DAT_ALIGN_R;
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ADC_InitStructure.ChsNumber = 1;
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ADC_Init((ADC_Module*)config->adc_periph, &ADC_InitStructure);
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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/* Enable ADC */
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ADC_Enable((ADC_Module*)config->adc_periph, ENABLE);
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2022-10-20 09:40:14 +08:00
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2022-07-13 19:56:14 +08:00
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/* Check ADC Ready */
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2022-10-20 09:40:14 +08:00
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while (ADC_GetFlagStatusNew((ADC_Module*)config->adc_periph, ADC_FLAG_RDY) == RESET);
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2022-07-13 19:56:14 +08:00
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/* Start ADC calibration */
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ADC_StartCalibration((ADC_Module*)config->adc_periph);
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2022-10-20 09:40:14 +08:00
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2022-07-13 19:56:14 +08:00
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/* Check the end of ADC calibration */
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2022-10-20 09:40:14 +08:00
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while (ADC_GetCalibrationStatus((ADC_Module*)config->adc_periph));
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2022-07-13 19:56:14 +08:00
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}
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static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
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{
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if (channel > ADC_CH_18)
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{
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return RT_EINVAL;
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}
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return RT_EOK;
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}
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static rt_err_t n32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
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{
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struct n32_adc_config *config;
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RT_ASSERT(device != RT_NULL);
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if (channel > ADC_CH_18)
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{
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return RT_EINVAL;
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}
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config = (struct n32_adc_config *)(device->parent.user_data);
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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ADC_ConfigRegularChannel((ADC_Module*)config->adc_periph, channel, 1, ADC_SAMP_TIME_239CYCLES5);
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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/* Start ADC Software Conversion */
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ADC_EnableSoftwareStartConv((ADC_Module*)config->adc_periph, ENABLE);
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2022-10-20 09:40:14 +08:00
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while (ADC_GetFlagStatus((ADC_Module*)config->adc_periph, ADC_FLAG_ENDC)==0)
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2022-07-13 19:56:14 +08:00
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{
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}
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2022-10-20 09:40:14 +08:00
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2022-07-13 19:56:14 +08:00
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ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_ENDC);
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ADC_ClearFlag((ADC_Module*)config->adc_periph, ADC_FLAG_STR);
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2022-10-20 09:40:14 +08:00
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*value = ADC_GetDat((ADC_Module*)config->adc_periph);
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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return RT_EOK;
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}
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static struct rt_adc_ops n32_adc_ops =
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{
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.enabled = n32_adc_enabled,
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.convert = n32_adc_convert,
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};
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int rt_hw_adc_init(void)
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{
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2022-10-20 09:40:14 +08:00
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GPIO_InitType GPIO_InitStructure;
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2022-07-13 19:56:14 +08:00
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int i = 0;
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int result = RT_EOK;
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2023-01-05 14:45:17 +08:00
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#if defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) || defined(SOC_N32G4FR)
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2022-10-20 09:40:14 +08:00
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#ifdef BSP_USING_ADC
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
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RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC, ENABLE);
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GPIO_InitStruct(&GPIO_InitStructure);
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/* Configure PA.01 PA.02 as analog input */
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GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Analog;
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GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
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#endif
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#endif
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#ifdef BSP_USING_ADC1
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
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2022-07-13 19:56:14 +08:00
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RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC1, ENABLE);
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2022-10-20 09:40:14 +08:00
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GPIO_InitStruct(&GPIO_InitStructure);
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/* Configure PA.01 PA.03 as analog input */
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GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_3;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
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2022-07-13 19:56:14 +08:00
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#endif /* BSP_USING_ADC1 */
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2022-07-23 11:53:42 +08:00
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2022-10-20 09:40:14 +08:00
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#ifdef BSP_USING_ADC2
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
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2022-07-13 19:56:14 +08:00
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RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC2, ENABLE);
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2022-07-23 11:53:42 +08:00
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2022-10-20 09:40:14 +08:00
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GPIO_InitStruct(&GPIO_InitStructure);
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/* Configure PA.04 PA.05 as analog input */
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GPIO_InitStructure.Pin = GPIO_PIN_4 | GPIO_PIN_5;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure);
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#endif /* BSP_USING_ADC2 */
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#ifdef BSP_USING_ADC3
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
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2022-07-13 19:56:14 +08:00
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RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC3, ENABLE);
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2022-10-20 09:40:14 +08:00
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GPIO_InitStruct(&GPIO_InitStructure);
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/* Configure PB.11 PB.13 as analog input */
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GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
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2022-07-13 19:56:14 +08:00
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#endif /* BSP_USING_ADC3 */
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2022-10-20 09:40:14 +08:00
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#ifdef BSP_USING_ADC4
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
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2022-07-13 19:56:14 +08:00
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RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_ADC4, ENABLE);
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2022-10-20 09:40:14 +08:00
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GPIO_InitStruct(&GPIO_InitStructure);
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/* Configure PB.14 PB.15 as analog input */
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GPIO_InitStructure.Pin = GPIO_PIN_14 | GPIO_PIN_15;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
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2022-07-13 19:56:14 +08:00
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#endif /* BSP_USING_ADC4 */
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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/* RCC_ADCHCLK_DIV16*/
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ADC_ConfigClk(ADC_CTRL3_CKMOD_AHB, RCC_ADCHCLK_DIV16);
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2022-10-20 09:40:14 +08:00
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/* Selsect HSE as RCC ADC1M CLK Source */
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RCC_ConfigAdc1mClk(RCC_ADC1MCLK_SRC_HSE, RCC_ADC1MCLK_DIV8);
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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for (i = 0; i < sizeof(adc_obj) / sizeof(adc_obj[0]); i++)
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{
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adc_obj[i].config = &adc_config[i];
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n32_adc_init(&adc_config[i]);
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rt_hw_adc_register(&adc_obj[i].adc_device, \
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adc_obj[i].config->name, &n32_adc_ops, adc_obj[i].config);
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}
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return result;
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}
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INIT_DEVICE_EXPORT(rt_hw_adc_init);
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2022-07-23 11:53:42 +08:00
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#endif /* defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) || defined(BSP_USING_ADC4) */
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2022-07-13 19:56:14 +08:00
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#endif /* RT_USING_ADC */
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