510 lines
23 KiB
C
510 lines
23 KiB
C
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
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*
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* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
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*
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* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
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*
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* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
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*
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* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
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*
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*/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v7.0
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processor: MIMXRT1062xxxxA
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package_id: MIMXRT1062DVL6A
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mcu_data: ksdk2_0
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processor_version: 8.0.3
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board: MIMXRT1060-EVK
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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#include "clock_config.h"
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#include "fsl_iomuxc.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockRUN();
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}
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockRUN
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called_from_default_init: true
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outputs:
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- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
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- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
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- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
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- {id: CLK_1M.outFreq, value: 1 MHz}
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- {id: CLK_24M.outFreq, value: 24 MHz}
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- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
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- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
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- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
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- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
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- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
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- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
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- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
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- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
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- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
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- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
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- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
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- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
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- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
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- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
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- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
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- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
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- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
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- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
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- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
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- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
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- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
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- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
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- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
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- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
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- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
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- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
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- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
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- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
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- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
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settings:
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- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
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- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
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- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
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- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
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- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
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- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
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- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
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- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
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- {id: CCM.SEMC_PODF.scale, value: '8'}
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- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
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- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
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- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
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- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
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- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
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- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
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- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
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- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
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- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
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- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
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- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
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- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
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- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
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- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
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- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
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- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
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- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
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- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
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- {id: CCM_ANALOG.PLL4.denom, value: '50'}
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- {id: CCM_ANALOG.PLL4.div, value: '47'}
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- {id: CCM_ANALOG.PLL5.denom, value: '1'}
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- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
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- {id: CCM_ANALOG.PLL5.num, value: '0'}
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- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
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- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
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- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
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- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
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- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
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- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
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sources:
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- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/*******************************************************************************
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
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{
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.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
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{
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.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
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.numerator = 0, /* 30 bit numerator of fractional loop divider */
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.denominator = 1, /* 30 bit denominator of fractional loop divider */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
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{
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.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
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{
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.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
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.postDivider = 8, /* Divider after PLL */
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.numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
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.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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/*******************************************************************************
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* Code for BOARD_BootClockRUN configuration
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******************************************************************************/
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void BOARD_BootClockRUN(void)
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{
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/* Init RTC OSC clock frequency. */
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CLOCK_SetRtcXtalFreq(32768U);
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/* Enable 1MHz clock output. */
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XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
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/* Use free 1MHz clock output. */
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XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
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/* Set XTAL 24MHz clock frequency. */
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CLOCK_SetXtalFreq(24000000U);
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/* Enable XTAL 24MHz clock source. */
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CLOCK_InitExternalClk(0);
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/* Enable internal RC. */
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CLOCK_InitRcOsc24M();
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/* Switch clock source to external OSC. */
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CLOCK_SwitchOsc(kCLOCK_XtalOsc);
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/* Set Oscillator ready counter value. */
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CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
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/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
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CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
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CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
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/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
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DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
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/* Waiting for DCDC_STS_DC_OK bit is asserted */
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while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
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{
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}
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/* Set AHB_PODF. */
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CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
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/* Disable IPG clock gate. */
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CLOCK_DisableClock(kCLOCK_Adc1);
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CLOCK_DisableClock(kCLOCK_Adc2);
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CLOCK_DisableClock(kCLOCK_Xbar1);
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CLOCK_DisableClock(kCLOCK_Xbar2);
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CLOCK_DisableClock(kCLOCK_Xbar3);
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/* Set IPG_PODF. */
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CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
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/* Set ARM_PODF. */
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CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
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/* Set PERIPH_CLK2_PODF. */
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CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
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/* Disable PERCLK clock gate. */
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CLOCK_DisableClock(kCLOCK_Gpt1);
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CLOCK_DisableClock(kCLOCK_Gpt1S);
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CLOCK_DisableClock(kCLOCK_Gpt2);
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CLOCK_DisableClock(kCLOCK_Gpt2S);
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CLOCK_DisableClock(kCLOCK_Pit);
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/* Set PERCLK_PODF. */
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CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
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/* Disable USDHC1 clock gate. */
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CLOCK_DisableClock(kCLOCK_Usdhc1);
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/* Set USDHC1_PODF. */
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CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
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/* Set Usdhc1 clock source. */
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CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
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/* Disable USDHC2 clock gate. */
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CLOCK_DisableClock(kCLOCK_Usdhc2);
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/* Set USDHC2_PODF. */
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CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
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/* Set Usdhc2 clock source. */
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CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
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/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
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* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
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#ifndef SKIP_SYSCLK_INIT
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/* Disable Semc clock gate. */
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CLOCK_DisableClock(kCLOCK_Semc);
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/* Set SEMC_PODF. */
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CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
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/* Set Semc alt clock source. */
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CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
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/* Set Semc clock source. */
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CLOCK_SetMux(kCLOCK_SemcMux, 0);
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#endif
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/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
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* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
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#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
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/* Disable Flexspi clock gate. */
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CLOCK_DisableClock(kCLOCK_FlexSpi);
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/* Set FLEXSPI_PODF. */
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CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
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/* Set Flexspi clock source. */
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CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
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#endif
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/* Disable Flexspi2 clock gate. */
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CLOCK_DisableClock(kCLOCK_FlexSpi2);
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/* Set FLEXSPI2_PODF. */
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CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
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/* Set Flexspi2 clock source. */
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CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
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/* Disable CSI clock gate. */
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CLOCK_DisableClock(kCLOCK_Csi);
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/* Set CSI_PODF. */
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CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
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/* Set Csi clock source. */
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CLOCK_SetMux(kCLOCK_CsiMux, 0);
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/* Disable LPSPI clock gate. */
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CLOCK_DisableClock(kCLOCK_Lpspi1);
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CLOCK_DisableClock(kCLOCK_Lpspi2);
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CLOCK_DisableClock(kCLOCK_Lpspi3);
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CLOCK_DisableClock(kCLOCK_Lpspi4);
|
||
|
|
/* Set LPSPI_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
|
||
|
|
/* Set Lpspi clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
|
||
|
|
/* Disable TRACE clock gate. */
|
||
|
|
CLOCK_DisableClock(kCLOCK_Trace);
|
||
|
|
/* Set TRACE_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
|
||
|
|
/* Set Trace clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_TraceMux, 0);
|
||
|
|
/* Disable SAI1 clock gate. */
|
||
|
|
CLOCK_DisableClock(kCLOCK_Sai1);
|
||
|
|
/* Set SAI1_CLK_PRED. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
|
||
|
|
/* Set SAI1_CLK_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
|
||
|
|
/* Set Sai1 clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
|
||
|
|
/* Disable SAI2 clock gate. */
|
||
|
|
CLOCK_DisableClock(kCLOCK_Sai2);
|
||
|
|
/* Set SAI2_CLK_PRED. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
|
||
|
|
/* Set SAI2_CLK_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
|
||
|
|
/* Set Sai2 clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
|
||
|
|
/* Disable SAI3 clock gate. */
|
||
|
|
CLOCK_DisableClock(kCLOCK_Sai3);
|
||
|
|
/* Set SAI3_CLK_PRED. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
|
||
|
|
/* Set SAI3_CLK_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
|
||
|
|
/* Set Sai3 clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
|
||
|
|
/* Disable Lpi2c clock gate. */
|
||
|
|
CLOCK_DisableClock(kCLOCK_Lpi2c1);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Lpi2c2);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Lpi2c3);
|
||
|
|
/* Set LPI2C_CLK_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
|
||
|
|
/* Set Lpi2c clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
|
||
|
|
/* Disable CAN clock gate. */
|
||
|
|
CLOCK_DisableClock(kCLOCK_Can1);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Can2);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Can3);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Can1S);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Can2S);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Can3S);
|
||
|
|
/* Set CAN_CLK_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
|
||
|
|
/* Set Can clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_CanMux, 2);
|
||
|
|
/* Disable UART clock gate. */
|
||
|
|
CLOCK_DisableClock(kCLOCK_Lpuart1);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Lpuart2);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Lpuart3);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Lpuart4);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Lpuart5);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Lpuart6);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Lpuart7);
|
||
|
|
CLOCK_DisableClock(kCLOCK_Lpuart8);
|
||
|
|
/* Set UART_CLK_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
|
||
|
|
/* Set Uart clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_UartMux, 0);
|
||
|
|
/* Disable LCDIF clock gate. */
|
||
|
|
CLOCK_DisableClock(kCLOCK_LcdPixel);
|
||
|
|
/* Set LCDIF_PRED. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
|
||
|
|
/* Set LCDIF_CLK_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
|
||
|
|
/* Set Lcdif pre clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
|
||
|
|
/* Disable SPDIF clock gate. */
|
||
|
|
CLOCK_DisableClock(kCLOCK_Spdif);
|
||
|
|
/* Set SPDIF0_CLK_PRED. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
|
||
|
|
/* Set SPDIF0_CLK_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
|
||
|
|
/* Set Spdif clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
|
||
|
|
/* Disable Flexio1 clock gate. */
|
||
|
|
CLOCK_DisableClock(kCLOCK_Flexio1);
|
||
|
|
/* Set FLEXIO1_CLK_PRED. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
|
||
|
|
/* Set FLEXIO1_CLK_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
|
||
|
|
/* Set Flexio1 clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
|
||
|
|
/* Disable Flexio2 clock gate. */
|
||
|
|
CLOCK_DisableClock(kCLOCK_Flexio2);
|
||
|
|
/* Set FLEXIO2_CLK_PRED. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
|
||
|
|
/* Set FLEXIO2_CLK_PODF. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
|
||
|
|
/* Set Flexio2 clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
|
||
|
|
/* Set Pll3 sw clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
|
||
|
|
/* Init ARM PLL. */
|
||
|
|
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
|
||
|
|
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
|
||
|
|
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
|
||
|
|
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
|
||
|
|
#ifndef SKIP_SYSCLK_INIT
|
||
|
|
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||
|
|
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
|
||
|
|
#endif
|
||
|
|
/* Init System PLL. */
|
||
|
|
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
|
||
|
|
/* Init System pfd0. */
|
||
|
|
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
|
||
|
|
/* Init System pfd1. */
|
||
|
|
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
|
||
|
|
/* Init System pfd2. */
|
||
|
|
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
|
||
|
|
/* Init System pfd3. */
|
||
|
|
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
|
||
|
|
#endif
|
||
|
|
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
|
||
|
|
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
|
||
|
|
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
|
||
|
|
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
|
||
|
|
/* Init Usb1 PLL. */
|
||
|
|
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
|
||
|
|
/* Init Usb1 pfd0. */
|
||
|
|
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
|
||
|
|
/* Init Usb1 pfd1. */
|
||
|
|
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
|
||
|
|
/* Init Usb1 pfd2. */
|
||
|
|
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
|
||
|
|
/* Init Usb1 pfd3. */
|
||
|
|
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
|
||
|
|
/* Disable Usb1 PLL output for USBPHY1. */
|
||
|
|
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
|
||
|
|
#endif
|
||
|
|
/* DeInit Audio PLL. */
|
||
|
|
CLOCK_DeinitAudioPll();
|
||
|
|
/* Bypass Audio PLL. */
|
||
|
|
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
|
||
|
|
/* Set divider for Audio PLL. */
|
||
|
|
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
|
||
|
|
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
|
||
|
|
/* Enable Audio PLL output. */
|
||
|
|
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
|
||
|
|
/* Init Video PLL. */
|
||
|
|
uint32_t pllVideo;
|
||
|
|
/* Disable Video PLL output before initial Video PLL. */
|
||
|
|
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
|
||
|
|
/* Bypass PLL first */
|
||
|
|
CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
|
||
|
|
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
|
||
|
|
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
|
||
|
|
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
|
||
|
|
pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
|
||
|
|
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
|
||
|
|
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
|
||
|
|
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
|
||
|
|
CCM_ANALOG->PLL_VIDEO = pllVideo;
|
||
|
|
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
/* Disable bypass for Video PLL. */
|
||
|
|
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
|
||
|
|
/* DeInit Enet PLL. */
|
||
|
|
CLOCK_DeinitEnetPll();
|
||
|
|
/* Bypass Enet PLL. */
|
||
|
|
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
|
||
|
|
/* Set Enet output divider. */
|
||
|
|
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
|
||
|
|
/* Enable Enet output. */
|
||
|
|
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
|
||
|
|
/* Set Enet2 output divider. */
|
||
|
|
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
|
||
|
|
/* Enable Enet2 output. */
|
||
|
|
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
|
||
|
|
/* Enable Enet25M output. */
|
||
|
|
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
|
||
|
|
/* DeInit Usb2 PLL. */
|
||
|
|
CLOCK_DeinitUsb2Pll();
|
||
|
|
/* Bypass Usb2 PLL. */
|
||
|
|
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
|
||
|
|
/* Enable Usb2 PLL output. */
|
||
|
|
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
|
||
|
|
/* Set preperiph clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
|
||
|
|
/* Set periph clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
|
||
|
|
/* Set periph clock2 clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
|
||
|
|
/* Set per clock source. */
|
||
|
|
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
|
||
|
|
/* Set lvds1 clock source. */
|
||
|
|
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
|
||
|
|
/* Set clock out1 divider. */
|
||
|
|
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
|
||
|
|
/* Set clock out1 source. */
|
||
|
|
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
|
||
|
|
/* Set clock out2 divider. */
|
||
|
|
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
|
||
|
|
/* Set clock out2 source. */
|
||
|
|
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
|
||
|
|
/* Set clock out1 drives clock out1. */
|
||
|
|
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
|
||
|
|
/* Disable clock out1. */
|
||
|
|
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
|
||
|
|
/* Disable clock out2. */
|
||
|
|
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
|
||
|
|
/* Set SAI1 MCLK1 clock source. */
|
||
|
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
|
||
|
|
/* Set SAI1 MCLK2 clock source. */
|
||
|
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
|
||
|
|
/* Set SAI1 MCLK3 clock source. */
|
||
|
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
|
||
|
|
/* Set SAI2 MCLK3 clock source. */
|
||
|
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
|
||
|
|
/* Set SAI3 MCLK3 clock source. */
|
||
|
|
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||
|
|
/* Set MQS configuration. */
|
||
|
|
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||
|
|
/* Set ENET1 Tx clock source. */
|
||
|
|
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
|
||
|
|
/* Set ENET2 Tx clock source. */
|
||
|
|
#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0)))
|
||
|
|
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false);
|
||
|
|
#else
|
||
|
|
IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false);
|
||
|
|
#endif
|
||
|
|
/* Set GPT1 High frequency reference clock source. */
|
||
|
|
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
|
||
|
|
/* Set GPT2 High frequency reference clock source. */
|
||
|
|
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
|
||
|
|
/* Set SystemCoreClock variable. */
|
||
|
|
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||
|
|
}
|
||
|
|
|