2022-11-10 22:22:48 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Email: opensource_embedded@phytium.com.cn
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*
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* Change Logs:
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* Date Author Notes
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2023-08-02 13:27:09 +08:00
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* 2022-10-26 huanghe first commit
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* 2023-07-27 zhugengyu flush cache in aarch64-el2
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2022-11-10 22:22:48 +08:00
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*
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*/
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.global _boot
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.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
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.org 0
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.text
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.section .boot,"ax"
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_boot:
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2023-08-02 13:27:09 +08:00
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/* hard code aarch64 instruction to flush dcache, refer to rt-thread __asm_flush_dcache_all */
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.long 0xd2800000 /* mov x0, #0x0 // clean and invaildate d-cache */
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.long 0x1400001a /* b <InvalidateFlushDcaches> */
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InvalidateFlushDcacheLevel:
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.long 0xd37ff80c /* lsl x12, x0, #1 */
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.long 0xd51a000c /* msr csselr_el1, x12 */
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.long 0xd5033fdf /* isb */
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.long 0xd5390006 /* mrs x6, ccsidr_el1 */
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.long 0x924008c2 /* and x2, x6, #0x7 */
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.long 0x91001042 /* add x2, x2, #0x4 */
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.long 0xd2807fe3 /* mov x3, #0x3ff */
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.long 0x8a460c63 /* and x3, x3, x6, lsr #3 */
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.long 0x5ac01065 /* clz w5, w3 */
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.long 0xd28fffe4 /* mov x4, #0x7fff */
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.long 0x8a463484 /* and x4, x4, x6, lsr #13 */
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InvalidateFlushCacheSet:
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.long 0xaa0303e6 /* mov x6, x3 */
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InvalidateFlushCacheWay:
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.long 0x9ac520c7 /* lsl x7, x6, x5 */
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.long 0xaa070189 /* orr x9, x12, x7 */
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.long 0x9ac22087 /* lsl x7, x4, x2 */
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.long 0xaa070129 /* orr x9, x9, x7 */
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.long 0x36000061 /* tbz w1, #0, <InvalidateFlushCacheWay+0x1c> */
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.long 0xd5087649 /* dc isw, x9 */
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.long 0x14000002 /* b <InvalidateFlushCacheWay+0x20> */
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.long 0xd5087e49 /* dc cisw, x9 */
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.long 0xf10004c6 /* subs x6, x6, #0x1 */
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.long 0x54fffeea /* b.ge <InvalidateFlushCacheWay> */
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.long 0xf1000484 /* subs x4, x4, #0x1 */
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.long 0x54fffe8a /* b.ge <InvalidateFlushCacheSet> */
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.long 0xd65f03c0 /* ret */
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InvalidateFlushDcaches:
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.long 0xaa0003e1 /* mov x1, x0 */
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.long 0xd5033f9f /* dsb sy */
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.long 0xd539002a /* mrs x10, clidr_el1 */
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.long 0xd358fd4b /* lsr x11, x10, #24 */
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.long 0x9240096b /* and x11, x11, #0x7 */
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.long 0xb400024b /* cbz x11, <InvalidateFlushDcacheEnd> */
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.long 0xaa1e03ef /* mov x15, x30 */
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.long 0xd2800000 /* mov x0, #0x0 */
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InvalidateFlushCachesLoopLevel:
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.long 0xd37ff80c /* lsl x12, x0, #1 */
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.long 0x8b00018c /* add x12, x12, x0 */
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.long 0x9acc254c /* lsr x12, x10, x12 */
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.long 0x9240098c /* and x12, x12, #0x7 */
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.long 0xf100099f /* cmp x12, #0x2 */
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.long 0x5400004b /* b.lt <InvalidateFlushCachesSkipLevel> */
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.long 0x97ffffd9 /* bl <InvalidateFlushDcacheLevel> */
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InvalidateFlushCachesSkipLevel:
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.long 0x91000400 /* add x0, x0, #0x1 */
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.long 0xeb00017f /* cmp x11, x0 */
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.long 0x54fffeec /* b.gt <InvalidateFlushCachesLoopLevel> */
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.long 0xd2800000 /* mov x0, #0x0 */
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.long 0xd51a0000 /* msr csselr_el1, x0 */
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.long 0xd5033f9f /* dsb sy */
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.long 0xd5033fdf /* isb */
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.long 0xaa0f03fe /* mov x30, x15 */
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InvalidateFlushDcacheEnd:
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/***************************************************************/
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/* switch from aarch64-el2 to aarch32-el1 */
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2022-11-10 22:22:48 +08:00
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Startup_Aarch32:
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.long 0xd5384240 /* mrs x0, currentel */
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.long 0xd342fc00 /* lsr x0, x0, #2 */
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.long 0x92400400 /* and x0, x0, #0x3 */
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.long 0xf1000c1f /* cmp x0, #0x3 */
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.long 0x540003a1 /* b.ne 1d0080c4 <el2_mode> */
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el3_mode:
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.long 0xd53ecca0 /* mrs x0, s3_6_c12_c12_5 - ICC_SRE_EL3 */
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.long 0xb2400c00 /* orr x0, x0, #0xf */
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.long 0xd51ecca0 /* msr s3_6_c12_c12_5, x0 */
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.long 0xd5033fdf /* isb */
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.long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */
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.long 0xb2400c00 /* orr x0, x0, #0xf */
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.long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */
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.long 0xd5033fdf /* isb */
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.long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */
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.long 0xb2400000 /* orr x0, x0, #0x1 */
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.long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */
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.long 0xd5033fdf /* isb */
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.long 0xd2803620 /* mov x0, #0x1b1 */
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.long 0xd51e1100 /* msr scr_el3, x0 */
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.long 0xd2867fe0 /* mov x0, #0x33ff */
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.long 0xd51c1140 /* msr cptr_el2, x0 */
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.long 0xd2810000 /* mov x0, #0x800 */
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.long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */
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.long 0xd5181000 /* msr sctlr_el1, x0 */
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.long 0x910003e0 /* mov x0, sp */
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.long 0xd51c4100 /* msr sp_el1, x0 */
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.long 0xd53ec000 /* mrs x0, vbar_el3 */
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.long 0xd518c000 /* msr vbar_el1, x0 */
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.long 0xd2803a60 /* mov x0, #0x1d3 */
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.long 0xd51e4000 /* msr spsr_el3, x0 */
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.long 0x10000500 /* adr x0, 1d008158 <el1_mode> */
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.long 0xd51e4020 /* msr elr_el3, x0 */
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.long 0xd69f03e0 /* eret */
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el2_mode:
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.long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */
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.long 0xb2400c00 /* orr x0, x0, #0xf */
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.long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */
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.long 0xd5033fdf /* isb */
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.long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */
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.long 0xb2400000 /* orr x0, x0, #0x1 */
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.long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */
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.long 0xd5033fdf /* isb */
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.long 0xd53ce100 /* mrs x0, cnthctl_el2 */
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.long 0xb2400400 /* orr x0, x0, #0x3 */
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.long 0xd51ce100 /* msr cnthctl_el2, x0 */
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.long 0xd51ce07f /* msr cntvoff_el2, xzr */
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.long 0xd5380000 /* mrs x0, midr_el1 */
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.long 0xd53800a1 /* mrs x1, mpidr_el1 */
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.long 0xd51c0000 /* msr vpidr_el2, x0 */
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.long 0xd51c00a1 /* msr vmpidr_el2, x1 */
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.long 0xd2867fe0 /* mov x0, #0x33ff */
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.long 0xd51c1140 /* msr cptr_el2, x0 */
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.long 0xd51c117f /* msr hstr_el2, xzr */
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.long 0xd2a00600 /* mov x0, #0x300000 */
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.long 0xd5181040 /* msr cpacr_el1, x0 */
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.long 0xd2800000 /* mov x0, #0x0 */
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.long 0xb2630000 /* orr x0, x0, #0x20000000 */
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.long 0xd51c1100 /* msr hcr_el2, x0 */
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.long 0xd53c1100 /* mrs x0, hcr_el2 */
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.long 0xd2810000 /* mov x0, #0x800 */
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.long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */
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.long 0xd5181000 /* msr sctlr_el1, x0 */
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.long 0x910003e0 /* mov x0, sp */
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.long 0xd51c4100 /* msr sp_el1, x0 */
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.long 0xd53cc000 /* mrs x0, vbar_el2 */
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.long 0xd518c000 /* msr vbar_el1, x0 */
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.long 0xd2803a60 /* mov x0, #0x1d3 */
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.long 0xd51c4000 /* msr spsr_el2, x0 */
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.long 0x10000060 /* adr x0, 1d008158 <el1_mode> */
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.long 0xd51c4020 /* msr elr_el2, x0 */
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.long 0xd69f03e0 /* eret */
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el1_mode:
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mov r0, #0
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mov r1, #0
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mov r2, #0
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mov r3, #0
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mov r4, #0
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mov r5, #0
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mov r6, #0
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mov r7, #0
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mov r8, #0
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mov r9, #0
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mov r10, #0
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mov r11, #0
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mov r12, #0
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mcr p15, 0, r0, c1, c0, 0 /* reset control register */
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isb
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/* enable vfp, therefore f_prink workable */
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vmrs r1, FPEXC /* read the exception register */
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orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
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vmsr FPEXC, r1 /* write back the exception register */
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bl system_vectors /* jump to libcpu/arm/cortex-a/vector_gcc.S */
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