119 lines
6.0 KiB
C
119 lines
6.0 KiB
C
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//*****************************************************************************
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//
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// hw_memmap.h - Macros defining the memory map of Stellaris.
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//
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// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program. Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 4694 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_MEMMAP_H__
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#define __HW_MEMMAP_H__
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//*****************************************************************************
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//
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// The following are defines for the base address of the memories and
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// peripherals.
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//
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//*****************************************************************************
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#define FLASH_BASE 0x00000000 // FLASH memory
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#define SRAM_BASE 0x20000000 // SRAM memory
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#define WATCHDOG0_BASE 0x40000000 // Watchdog0
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#define WATCHDOG1_BASE 0x40001000 // Watchdog1
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#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
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#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
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#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
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#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
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#define SSI0_BASE 0x40008000 // SSI0
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#define SSI1_BASE 0x40009000 // SSI1
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#define UART0_BASE 0x4000C000 // UART0
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#define UART1_BASE 0x4000D000 // UART1
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#define UART2_BASE 0x4000E000 // UART2
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#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
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#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
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#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
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#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
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#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
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#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
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#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
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#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
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#define PWM_BASE 0x40028000 // PWM
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#define QEI0_BASE 0x4002C000 // QEI0
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#define QEI1_BASE 0x4002D000 // QEI1
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#define TIMER0_BASE 0x40030000 // Timer0
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#define TIMER1_BASE 0x40031000 // Timer1
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#define TIMER2_BASE 0x40032000 // Timer2
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#define TIMER3_BASE 0x40033000 // Timer3
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#define ADC0_BASE 0x40038000 // ADC0
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#define ADC1_BASE 0x40039000 // ADC1
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#define COMP_BASE 0x4003C000 // Analog comparators
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#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
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#define CAN0_BASE 0x40040000 // CAN0
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#define CAN1_BASE 0x40041000 // CAN1
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#define CAN2_BASE 0x40042000 // CAN2
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#define ETH_BASE 0x40048000 // Ethernet
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#define MAC_BASE 0x40048000 // Ethernet
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#define USB0_BASE 0x40050000 // USB 0 Controller
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#define I2S0_BASE 0x40054000 // I2S0
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#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
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#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
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#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
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#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
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#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
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#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
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#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
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#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
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#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
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#define EPI0_BASE 0x400D0000 // EPI0
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#define HIB_BASE 0x400FC000 // Hibernation Module
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#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
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#define SYSCTL_BASE 0x400FE000 // System Control
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#define UDMA_BASE 0x400FF000 // uDMA Controller
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#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
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#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
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#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
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#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
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#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
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//*****************************************************************************
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//
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// The following definitions are deprecated.
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//
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//*****************************************************************************
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#ifndef DEPRECATED
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//*****************************************************************************
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//
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// The following are deprecated defines for the base address of the memories
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// and peripherals.
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//
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//*****************************************************************************
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#define WATCHDOG_BASE 0x40000000 // Watchdog
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#define SSI_BASE 0x40008000 // SSI
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#define I2C_MASTER_BASE 0x40020000 // I2C Master
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#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
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#define QEI_BASE 0x4002C000 // QEI
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#define ADC_BASE 0x40038000 // ADC
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#endif
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#endif // __HW_MEMMAP_H__
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