2017-08-29 19:30:21 +08:00
|
|
|
/*
|
|
|
|
* File : drv_spi.c
|
|
|
|
* This file is part of RT-Thread RTOS
|
|
|
|
* COPYRIGHT (C) 2017 RT-Thread Develop Team
|
|
|
|
*
|
|
|
|
* The license and distribution terms for this file may be
|
|
|
|
* found in the file LICENSE in this distribution or at
|
|
|
|
* http://www.rt-thread.org/license/LICENSE
|
|
|
|
*
|
|
|
|
* Change Logs:
|
|
|
|
* Date Author Notes
|
|
|
|
* 2017-06-05 tanek first implementation.
|
|
|
|
*/
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
#include "drv_spi.h"
|
|
|
|
|
|
|
|
#include <board.h>
|
|
|
|
#include <finsh.h>
|
|
|
|
|
2017-08-30 10:42:14 +08:00
|
|
|
#ifdef RT_USING_SPI
|
|
|
|
|
|
|
|
#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) && \
|
|
|
|
!defined(RT_USING_SPI2) && !defined(RT_USING_SPI3) && \
|
|
|
|
!defined(RT_USING_SPI4) && !defined(RT_USING_SPI5)
|
|
|
|
#error "Please define at least one SPIx"
|
|
|
|
#endif
|
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
//#define DEBUG
|
|
|
|
|
|
|
|
#define ARR_LEN(__N) (sizeof(__N) / sizeof(__N[0]))
|
|
|
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
|
|
|
|
#else
|
2021-03-12 00:03:36 +08:00
|
|
|
#define DEBUG_PRINTF(...)
|
2017-08-29 19:30:21 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* private rt-thread spi ops function */
|
|
|
|
static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
|
|
|
|
static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message);
|
|
|
|
|
2017-08-30 15:30:38 +08:00
|
|
|
static struct rt_spi_ops gd32_spi_ops =
|
2017-08-29 19:30:21 +08:00
|
|
|
{
|
|
|
|
configure,
|
|
|
|
xfer
|
|
|
|
};
|
|
|
|
|
|
|
|
static rt_err_t configure(struct rt_spi_device* device,
|
|
|
|
struct rt_spi_configuration* configuration)
|
|
|
|
{
|
2021-03-12 00:03:36 +08:00
|
|
|
struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
|
2017-08-30 15:30:38 +08:00
|
|
|
struct gd32f4_spi *f4_spi = (struct gd32f4_spi *)spi_bus->parent.user_data;
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
spi_parameter_struct spi_init_struct;
|
|
|
|
|
|
|
|
uint32_t spi_periph = f4_spi->spi_periph;
|
|
|
|
|
|
|
|
|
2021-03-12 00:03:36 +08:00
|
|
|
RT_ASSERT(device != RT_NULL);
|
|
|
|
RT_ASSERT(configuration != RT_NULL);
|
2017-08-29 19:30:21 +08:00
|
|
|
|
|
|
|
/* data_width */
|
|
|
|
if(configuration->data_width <= 8)
|
|
|
|
{
|
|
|
|
spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
|
|
|
|
}
|
|
|
|
else if(configuration->data_width <= 16)
|
|
|
|
{
|
|
|
|
spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
return RT_EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* baudrate */
|
|
|
|
{
|
|
|
|
rcu_clock_freq_enum spi_src;
|
|
|
|
uint32_t spi_apb_clock;
|
|
|
|
uint32_t max_hz;
|
|
|
|
|
|
|
|
max_hz = configuration->max_hz;
|
|
|
|
|
|
|
|
DEBUG_PRINTF("sys freq: %d\n", HAL_RCC_GetSysClockFreq());
|
|
|
|
DEBUG_PRINTF("pclk2 freq: %d\n", HAL_RCC_GetPCLK2Freq());
|
|
|
|
DEBUG_PRINTF("max freq: %d\n", max_hz);
|
|
|
|
|
|
|
|
if (spi_periph == SPI1 || spi_periph == SPI2)
|
|
|
|
{
|
|
|
|
spi_src = CK_APB1;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
spi_src = CK_APB2;
|
|
|
|
}
|
|
|
|
spi_apb_clock = rcu_clock_freq_get(spi_src);
|
|
|
|
|
|
|
|
if(max_hz >= spi_apb_clock/2)
|
|
|
|
{
|
|
|
|
spi_init_struct.prescale = SPI_PSC_2;
|
|
|
|
}
|
|
|
|
else if (max_hz >= spi_apb_clock/4)
|
|
|
|
{
|
|
|
|
spi_init_struct.prescale = SPI_PSC_4;
|
|
|
|
}
|
|
|
|
else if (max_hz >= spi_apb_clock/8)
|
|
|
|
{
|
|
|
|
spi_init_struct.prescale = SPI_PSC_8;
|
|
|
|
}
|
|
|
|
else if (max_hz >= spi_apb_clock/16)
|
|
|
|
{
|
|
|
|
spi_init_struct.prescale = SPI_PSC_16;
|
|
|
|
}
|
|
|
|
else if (max_hz >= spi_apb_clock/32)
|
|
|
|
{
|
|
|
|
spi_init_struct.prescale = SPI_PSC_32;
|
|
|
|
}
|
|
|
|
else if (max_hz >= spi_apb_clock/64)
|
|
|
|
{
|
|
|
|
spi_init_struct.prescale = SPI_PSC_64;
|
|
|
|
}
|
|
|
|
else if (max_hz >= spi_apb_clock/128)
|
|
|
|
{
|
|
|
|
spi_init_struct.prescale = SPI_PSC_128;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* min prescaler 256 */
|
|
|
|
spi_init_struct.prescale = SPI_PSC_256;
|
|
|
|
}
|
|
|
|
} /* baudrate */
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2020-12-03 08:48:07 +08:00
|
|
|
switch(configuration->mode & RT_SPI_MODE_3)
|
2017-08-29 19:30:21 +08:00
|
|
|
{
|
|
|
|
case RT_SPI_MODE_0:
|
|
|
|
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
|
|
|
|
break;
|
|
|
|
case RT_SPI_MODE_1:
|
|
|
|
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
|
2021-03-12 00:03:36 +08:00
|
|
|
break;
|
2017-08-29 19:30:21 +08:00
|
|
|
case RT_SPI_MODE_2:
|
|
|
|
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
|
2021-03-12 00:03:36 +08:00
|
|
|
break;
|
2017-08-29 19:30:21 +08:00
|
|
|
case RT_SPI_MODE_3:
|
|
|
|
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
|
|
|
|
break;
|
|
|
|
}
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
/* MSB or LSB */
|
|
|
|
if(configuration->mode & RT_SPI_MSB)
|
|
|
|
{
|
|
|
|
spi_init_struct.endian = SPI_ENDIAN_MSB;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
spi_init_struct.endian = SPI_ENDIAN_LSB;
|
|
|
|
}
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
|
|
|
|
spi_init_struct.device_mode = SPI_MASTER;
|
|
|
|
spi_init_struct.nss = SPI_NSS_SOFT;
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
spi_crc_off(spi_periph);
|
|
|
|
|
|
|
|
/* init SPI */
|
|
|
|
spi_init(spi_periph, &spi_init_struct);
|
|
|
|
/* Enable SPI_MASTER */
|
2021-03-12 00:03:36 +08:00
|
|
|
spi_enable(spi_periph);
|
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
return RT_EOK;
|
|
|
|
};
|
|
|
|
|
|
|
|
static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
|
|
|
|
{
|
2017-08-30 15:30:38 +08:00
|
|
|
struct rt_spi_bus * gd32_spi_bus = (struct rt_spi_bus *)device->bus;
|
|
|
|
struct gd32f4_spi *f4_spi = (struct gd32f4_spi *)gd32_spi_bus->parent.user_data;
|
2017-08-29 19:30:21 +08:00
|
|
|
struct rt_spi_configuration * config = &device->config;
|
2017-08-30 15:30:38 +08:00
|
|
|
struct gd32_spi_cs * gd32_spi_cs = device->parent.user_data;
|
2017-08-29 19:30:21 +08:00
|
|
|
uint32_t spi_periph = f4_spi->spi_periph;
|
|
|
|
|
2021-03-12 00:03:36 +08:00
|
|
|
RT_ASSERT(device != NULL);
|
|
|
|
RT_ASSERT(message != NULL);
|
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
/* take CS */
|
|
|
|
if(message->cs_take)
|
|
|
|
{
|
2017-08-30 15:30:38 +08:00
|
|
|
gpio_bit_reset(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
|
2017-08-29 19:30:21 +08:00
|
|
|
DEBUG_PRINTF("spi take cs\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
{
|
|
|
|
if(config->data_width <= 8)
|
|
|
|
{
|
|
|
|
const rt_uint8_t * send_ptr = message->send_buf;
|
|
|
|
rt_uint8_t * recv_ptr = message->recv_buf;
|
|
|
|
rt_uint32_t size = message->length;
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
DEBUG_PRINTF("spi poll transfer start: %d\n", size);
|
|
|
|
|
|
|
|
while(size--)
|
|
|
|
{
|
|
|
|
rt_uint8_t data = 0xFF;
|
|
|
|
|
|
|
|
if(send_ptr != RT_NULL)
|
|
|
|
{
|
|
|
|
data = *send_ptr++;
|
|
|
|
}
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-30 15:30:38 +08:00
|
|
|
// Todo: replace register read/write by gd32f4 lib
|
2017-08-29 19:30:21 +08:00
|
|
|
//Wait until the transmit buffer is empty
|
|
|
|
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
|
|
|
|
// Send the byte
|
2021-03-12 00:03:36 +08:00
|
|
|
spi_i2s_data_transmit(spi_periph, data);
|
2017-08-29 19:30:21 +08:00
|
|
|
|
|
|
|
//Wait until a data is received
|
|
|
|
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
|
|
|
|
// Get the received data
|
|
|
|
data = spi_i2s_data_receive(spi_periph);
|
|
|
|
|
|
|
|
if(recv_ptr != RT_NULL)
|
|
|
|
{
|
|
|
|
*recv_ptr++ = data;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
DEBUG_PRINTF("spi poll transfer finsh\n");
|
|
|
|
}
|
|
|
|
else if(config->data_width <= 16)
|
|
|
|
{
|
|
|
|
const rt_uint16_t * send_ptr = message->send_buf;
|
|
|
|
rt_uint16_t * recv_ptr = message->recv_buf;
|
|
|
|
rt_uint32_t size = message->length;
|
|
|
|
|
|
|
|
while(size--)
|
|
|
|
{
|
|
|
|
rt_uint16_t data = 0xFF;
|
|
|
|
|
|
|
|
if(send_ptr != RT_NULL)
|
|
|
|
{
|
|
|
|
data = *send_ptr++;
|
|
|
|
}
|
|
|
|
|
|
|
|
//Wait until the transmit buffer is empty
|
|
|
|
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
|
|
|
|
// Send the byte
|
2021-03-12 00:03:36 +08:00
|
|
|
spi_i2s_data_transmit(spi_periph, data);
|
2017-08-29 19:30:21 +08:00
|
|
|
|
|
|
|
//Wait until a data is received
|
|
|
|
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
|
|
|
|
// Get the received data
|
|
|
|
data = spi_i2s_data_receive(spi_periph);
|
|
|
|
|
|
|
|
if(recv_ptr != RT_NULL)
|
|
|
|
{
|
|
|
|
*recv_ptr++ = data;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* release CS */
|
|
|
|
if(message->cs_release)
|
|
|
|
{
|
2021-03-12 00:03:36 +08:00
|
|
|
gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
|
2017-08-29 19:30:21 +08:00
|
|
|
DEBUG_PRINTF("spi release cs\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
return message->length;
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static struct rt_spi_bus spi_bus[];
|
|
|
|
|
2017-08-30 15:30:38 +08:00
|
|
|
static const struct gd32f4_spi spis[] = {
|
2017-08-29 19:30:21 +08:00
|
|
|
#ifdef RT_USING_SPI0
|
|
|
|
{SPI0, RCU_SPI0, &spi_bus[0]},
|
|
|
|
#endif
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
#ifdef RT_USING_SPI1
|
|
|
|
{SPI1, RCU_SPI1, &spi_bus[1]},
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef RT_USING_SPI2
|
|
|
|
{SPI2, RCU_SPI2, &spi_bus[2]},
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef RT_USING_SPI3
|
|
|
|
{SPI3, RCU_SPI3, &spi_bus[3]},
|
|
|
|
#endif
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
#ifdef RT_USING_SPI4
|
|
|
|
{SPI4, RCU_SPI4, &spi_bus[4]},
|
|
|
|
#endif
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
#ifdef RT_USING_SPI5
|
|
|
|
{SPI5, RCU_SPI5, &spi_bus[5]},
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct rt_spi_bus spi_bus[ARR_LEN(spis)];
|
|
|
|
|
2017-08-30 15:30:38 +08:00
|
|
|
/** \brief init and register gd32 spi bus.
|
2017-08-29 19:30:21 +08:00
|
|
|
*
|
2017-08-30 15:30:38 +08:00
|
|
|
* \param SPI: gd32 SPI, e.g: SPI1,SPI2,SPI3.
|
2017-08-29 19:30:21 +08:00
|
|
|
* \param spi_bus_name: spi bus name, e.g: "spi1"
|
|
|
|
* \return
|
|
|
|
*
|
|
|
|
*/
|
2017-08-30 15:30:38 +08:00
|
|
|
rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
|
|
|
|
//struct gd32_spi_bus * gd32_spi,
|
2017-08-29 19:30:21 +08:00
|
|
|
const char * spi_bus_name)
|
|
|
|
{
|
|
|
|
int i;
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
RT_ASSERT(spi_bus_name != RT_NULL);
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
for (i = 0; i < ARR_LEN(spis); i++)
|
|
|
|
{
|
|
|
|
if (spi_periph == spis[i].spi_periph)
|
|
|
|
{
|
|
|
|
rcu_periph_clock_enable(spis[i].spi_clk);
|
|
|
|
spis[i].spi_bus->parent.user_data = (void *)&spis[i];
|
2017-08-30 15:30:38 +08:00
|
|
|
rt_spi_bus_register(spis[i].spi_bus, spi_bus_name, &gd32_spi_ops);
|
2017-08-29 19:30:21 +08:00
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
}
|
2021-03-12 00:03:36 +08:00
|
|
|
|
2017-08-29 19:30:21 +08:00
|
|
|
return RT_ERROR;
|
|
|
|
}
|
2017-08-30 10:42:14 +08:00
|
|
|
#endif
|