466 lines
22 KiB
C
466 lines
22 KiB
C
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//*****************************************************************************
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//
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// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
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//
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// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 8049 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_I2C_H__
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#define __HW_I2C_H__
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//*****************************************************************************
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//
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// The following are defines for the I2C register offsets.
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//
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//*****************************************************************************
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#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
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#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address
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#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status
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#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
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#define I2C_O_SDR 0x00000008 // I2C Slave Data
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#define I2C_O_MDR 0x00000008 // I2C Master Data
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#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
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#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask
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#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status
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#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
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#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
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#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt
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// Status
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#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear
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#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
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// Status
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#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
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#define I2C_O_SOAR2 0x0000001C // I2C Slave Own Address 2
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#define I2C_O_MCR 0x00000020 // I2C Master Configuration
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#define I2C_O_SACKCTL 0x00000020 // I2C ACK Control
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#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
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// Count
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#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
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#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_MSA register.
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//
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//*****************************************************************************
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#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
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#define I2C_MSA_RS 0x00000001 // Receive not send
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#define I2C_MSA_SA_S 1
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_SOAR register.
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//
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//*****************************************************************************
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#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
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#define I2C_SOAR_OAR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_SCSR register.
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//
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//*****************************************************************************
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#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
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#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
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#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
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#define I2C_SCSR_FBR 0x00000004 // First Byte Received
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#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
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#define I2C_SCSR_DA 0x00000001 // Device Active
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#define I2C_SCSR_RREQ 0x00000001 // Receive Request
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_MCS register.
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//
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//*****************************************************************************
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#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
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#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
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#define I2C_MCS_IDLE 0x00000020 // I2C Idle
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#define I2C_MCS_QCMD 0x00000020 // Quick Command
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#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
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#define I2C_MCS_HS 0x00000010 // High-Speed Enable
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#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
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#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
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#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
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#define I2C_MCS_STOP 0x00000004 // Generate STOP
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#define I2C_MCS_START 0x00000002 // Generate START
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#define I2C_MCS_ERROR 0x00000002 // Error
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#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
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#define I2C_MCS_BUSY 0x00000001 // I2C Busy
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_SDR register.
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//
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//*****************************************************************************
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#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
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#define I2C_SDR_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_MDR register.
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//
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//*****************************************************************************
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#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
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#define I2C_MDR_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_MTPR register.
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//
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//*****************************************************************************
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#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
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#define I2C_MTPR_TPR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_SIMR register.
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//
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//*****************************************************************************
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#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
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#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
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#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_SRIS register.
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//
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//*****************************************************************************
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#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
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// Status
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#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
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// Status
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#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_MIMR register.
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//
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//*****************************************************************************
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#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
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#define I2C_MIMR_IM 0x00000001 // Interrupt Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_MRIS register.
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//
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//*****************************************************************************
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#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
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// Status
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#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_SMIS register.
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//
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//*****************************************************************************
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#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
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// Status
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#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
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// Status
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#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_SICR register.
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//
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//*****************************************************************************
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#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
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#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
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#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_MMIS register.
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//
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//*****************************************************************************
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#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
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// Status
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#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_MICR register.
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//
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//*****************************************************************************
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#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
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#define I2C_MICR_IC 0x00000001 // Interrupt Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_SOAR2 register.
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//
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//*****************************************************************************
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#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
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#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
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#define I2C_SOAR2_OAR2_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_MCR register.
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//
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//*****************************************************************************
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#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
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#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
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#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_SACKCTL register.
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//
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//*****************************************************************************
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#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
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#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
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//
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//*****************************************************************************
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#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
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#define I2C_MCLKOCNT_CNTL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_MBMON register.
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//
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//*****************************************************************************
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#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
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#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2C_O_PP register.
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//
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//*****************************************************************************
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#define I2C_PP_HS 0x00000001 // High-Speed Capable
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//*****************************************************************************
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//
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// The following definitions are deprecated.
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//
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//*****************************************************************************
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#ifndef DEPRECATED
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//*****************************************************************************
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//
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// The following are deprecated defines for the I2C register offsets.
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//
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//*****************************************************************************
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#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the I2C_O_SIMR
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// register.
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//
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//*****************************************************************************
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#define I2C_SIMR_IM 0x00000001 // Interrupt Mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the I2C_O_SRIS
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// register.
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//
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//*****************************************************************************
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#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the I2C_O_SMIS
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// register.
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//
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//*****************************************************************************
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#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the I2C_O_SICR
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// register.
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//
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//*****************************************************************************
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#define I2C_SICR_IC 0x00000001 // Clear Interrupt
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//*****************************************************************************
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//
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// The following are deprecated defines for the I2C master register offsets.
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//
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//*****************************************************************************
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#define I2C_MASTER_O_SA 0x00000000 // Slave address register
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#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
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#define I2C_MASTER_O_DR 0x00000008 // Data register
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#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
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#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
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#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
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#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
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#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register
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#define I2C_MASTER_O_CR 0x00000020 // Configuration register
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//*****************************************************************************
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//
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// The following are deprecated defines for the I2C slave register offsets.
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//
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//*****************************************************************************
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#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
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#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
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#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
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#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
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#define I2C_SLAVE_O_DR 0x00000008 // Data register
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#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
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#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the I2C master
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// slave address register.
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//
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//*****************************************************************************
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#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
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#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
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#define I2C_MASTER_SA_SA_SHIFT 1
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the I2C Master
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// Control and Status register.
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//
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|
//*****************************************************************************
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#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
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||
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#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
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||
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|
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
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|
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
|
||
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|
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
|
||
|
|
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
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||
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#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
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||
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|
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
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|
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
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#define I2C_MASTER_CS_STOP 0x00000004 // Stop
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#define I2C_MASTER_CS_START 0x00000002 // Start
|
||
|
|
#define I2C_MASTER_CS_RUN 0x00000001 // Run
|
||
|
|
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||
|
|
//*****************************************************************************
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||
|
|
//
|
||
|
|
// The following are deprecated defines for the values used in determining the
|
||
|
|
// contents of the I2C Master Timer Period register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_SCL_FAST 400000 // SCL fast frequency
|
||
|
|
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
|
||
|
|
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
|
||
|
|
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
|
||
|
|
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are deprecated defines for the bit fields in the I2C Master
|
||
|
|
// Interrupt Mask register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are deprecated defines for the bit fields in the I2C Master
|
||
|
|
// Raw Interrupt Status register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are deprecated defines for the bit fields in the I2C Master
|
||
|
|
// Masked Interrupt Status register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are deprecated defines for the bit fields in the I2C Master
|
||
|
|
// Interrupt Clear register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are deprecated defines for the bit fields in the I2C Master
|
||
|
|
// Configuration register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
|
||
|
|
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
|
||
|
|
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are deprecated defines for the bit fields in the I2C Slave Own
|
||
|
|
// Address register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are deprecated defines for the bit fields in the I2C Slave
|
||
|
|
// Control/Status register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master
|
||
|
|
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
|
||
|
|
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
|
||
|
|
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are deprecated defines for the bit fields in the I2C Slave
|
||
|
|
// Interrupt Mask register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are deprecated defines for the bit fields in the I2C Slave Raw
|
||
|
|
// Interrupt Status register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are deprecated defines for the bit fields in the I2C Slave
|
||
|
|
// Masked Interrupt Status register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// The following are deprecated defines for the bit fields in the I2C Slave
|
||
|
|
// Interrupt Clear register.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif // __HW_I2C_H__
|