175 lines
3.8 KiB
ArmAsm
175 lines
3.8 KiB
ArmAsm
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/********************************** (C) COPYRIGHT *******************************
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* File Name : startup_gcc.s
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* Author : WCH
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* Version : V1.0
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* Date : 2020/07/31
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* Description : CH56x vector table for eclipse toolchain.
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*******************************************************************************/
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.section .init,"ax",@progbits
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.global _start
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.align 1
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_start:
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j handle_reset
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.section .vector,"ax",@progbits
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.align 1
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_vector_base:
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.option norvc;
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.word 0
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.word 0
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j nmi_handler
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j hardfault_handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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j systick_handler
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.word 0
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j swi_handler
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.word 0
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/* External Interrupts */
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j wdog_irq_handler
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j tmr0_irq_handler
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j gpio_irq_handler
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j spi0_irq_handler
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j usbss_irq_handler
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j link_irq_handler
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j tmr1_irq_handler
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j tmr2_irq_handler
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j uart0_irq_handler
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j usbhs_irq_handler
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j emmc_irq_handler
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j dvp_irq_handler
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j hspi_irq_handler
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j spi1_irq_handler
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j uart1_irq_handler
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j uart2_irq_handler
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j uart3_irq_handler
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j serdes_irq_handler
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j eth_irq_handler
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j pmt_irq_handler
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j ecdc_irq_handler
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.option rvc;
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.section .text.vector_handler,"ax", @prsocogbits
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.weak nmi_handler
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.weak hardfault_handler
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.weak systick_handler
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.weak swi_handler
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.weak wdog_irq_handler
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.weak tmr0_irq_handler
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.weak gpio_irq_handler
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.weak spi0_irq_handler
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.weak usbss_irq_handler
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.weak link_irq_handler
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.weak tmr1_irq_handler
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.weak tmr2_irq_handler
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.weak uart0_irq_handler
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.weak usbhs_irq_handler
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.weak emmc_irq_handler
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.weak dvp_irq_handler
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.weak hspi_irq_handler
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.weak spi1_irq_handler
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.weak uart1_irq_handler
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.weak uart2_irq_handler
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.weak uart3_irq_handler
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.weak serdes_irq_handler
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.weak eth_irq_handler
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.weak pmt_irq_handler
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.weak ecdc_irq_handler
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nmi_handler: j .L_rip
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hardfault_handler: j .L_rip
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systick_handler: j .L_rip
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swi_handler: j .L_rip
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wdog_irq_handler: j .L_rip
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tmr0_irq_handler: j .L_rip
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gpio_irq_handler: j .L_rip
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spi0_irq_handler: j .L_rip
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usbss_irq_handler: j .L_rip
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link_irq_handler: j .L_rip
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tmr1_irq_handler: j .L_rip
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tmr2_irq_handler: j .L_rip
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uart0_irq_handler: j .L_rip
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usbhs_irq_handler: j .L_rip
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emmc_irq_handler: j .L_rip
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dvp_irq_handler: j .L_rip
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hspi_irq_handler: j .L_rip
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spi1_irq_handler: j .L_rip
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uart1_irq_handler: j .L_rip
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uart2_irq_handler: j .L_rip
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uart3_irq_handler: j .L_rip
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serdes_irq_handler: j .L_rip
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eth_irq_handler: j .L_rip
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pmt_irq_handler: j .L_rip
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ecdc_irq_handler: j .L_rip
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.L_rip:
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csrr t0, mepc
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csrr t1, mstatus
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csrr t2, mcause
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csrr t3, mtval
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csrr t4, mscratch
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1: j 1b
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.section .text.handle_reset,"ax",@progbits
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.weak handle_reset
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.align 1
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handle_reset:
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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1:
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la sp, _eusrstack
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/* Load data section from flash to RAM */
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2:
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la a0, _data_lma
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la a1, _data_vma
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la a2, _edata
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bgeu a1, a2, 2f
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1:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, 1b
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/* clear bss section */
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2:
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la a0, _sbss
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la a1, _ebss
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bgeu a0, a1, 2f
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1:
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sw zero, (a0)
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addi a0, a0, 4
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bltu a0, a1, 1b
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/* clear dmadata section */
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2:
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la a0, _dmadata_start
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la a1, _dmadata_end
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bgeu a0, a1, 2f
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1:
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sw zero, (a0)
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addi a0, a0, 4
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bltu a0, a1, 1b
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2:
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/* leave all interrupt disabled */
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li t0, 0x1800
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csrs mstatus, t0
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la t0, _vector_base
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ori t0, t0, 1
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csrw mtvec, t0
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la t0, entry
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csrw mepc, t0
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mret
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