2022-05-06 09:28:21 +08:00
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/*
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* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-04-28 CDT first version
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*/
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#ifndef __SPI_CONFIG_H__
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#define __SPI_CONFIG_H__
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#include <rtthread.h>
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2022-05-15 20:57:35 +08:00
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#include "irq_config.h"
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2022-05-06 09:28:21 +08:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_SPI1
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#ifndef SPI1_BUS_CONFIG
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#define SPI1_BUS_CONFIG \
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{ \
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.Instance = CM_SPI1, \
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.bus_name = "spi1", \
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.clock = FCG1_PERIPH_SPI1, \
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}
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#endif /* SPI1_BUS_CONFIG */
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#endif /* BSP_USING_SPI1 */
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#ifdef BSP_SPI1_TX_USING_DMA
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#ifndef SPI1_TX_DMA_CONFIG
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#define SPI1_TX_DMA_CONFIG \
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{ \
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.Instance = SPI1_TX_DMA_INSTANCE, \
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.channel = SPI1_TX_DMA_CHANNEL, \
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.clock = SPI1_TX_DMA_CLOCK, \
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.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI1_SPTI, \
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.irq_config = \
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{ \
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.irq_num = SPI1_TX_DMA_IRQn, \
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.irq_prio = SPI1_TX_DMA_INT_PRIO, \
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.int_src = SPI1_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI1_TX_DMA_CONFIG */
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#endif /* BSP_SPI1_TX_USING_DMA */
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#ifdef BSP_SPI1_RX_USING_DMA
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#ifndef SPI1_RX_DMA_CONFIG
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#define SPI1_RX_DMA_CONFIG \
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{ \
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.Instance = SPI1_RX_DMA_INSTANCE, \
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.channel = SPI1_RX_DMA_CHANNEL, \
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.clock = SPI1_RX_DMA_CLOCK, \
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.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI1_SPRI, \
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.irq_config = \
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{ \
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.irq_num = SPI1_RX_DMA_IRQn, \
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.irq_prio = SPI1_RX_DMA_INT_PRIO, \
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.int_src = SPI1_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI1_RX_DMA_CONFIG */
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#endif /* BSP_SPI1_RX_USING_DMA */
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#ifdef BSP_USING_SPI2
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#ifndef SPI2_BUS_CONFIG
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#define SPI2_BUS_CONFIG \
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{ \
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.Instance = CM_SPI2, \
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.bus_name = "spi2", \
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.clock = FCG1_PERIPH_SPI2, \
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}
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#endif /* SPI2_BUS_CONFIG */
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#endif /* BSP_USING_SPI2 */
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#ifdef BSP_SPI2_TX_USING_DMA
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#ifndef SPI2_TX_DMA_CONFIG
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#define SPI2_TX_DMA_CONFIG \
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{ \
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.Instance = SPI2_TX_DMA_INSTANCE, \
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.channel = SPI2_TX_DMA_CHANNEL, \
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.clock = SPI2_TX_DMA_CLOCK, \
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.trigger_select = SPI2_TX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI2_SPTI, \
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.irq_config = \
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{ \
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.irq_num = SPI2_TX_DMA_IRQn, \
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.irq_prio = SPI2_TX_DMA_INT_PRIO, \
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.int_src = SPI2_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI2_TX_DMA_CONFIG */
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#endif /* BSP_SPI2_TX_USING_DMA */
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#ifdef BSP_SPI2_RX_USING_DMA
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#ifndef SPI2_RX_DMA_CONFIG
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#define SPI2_RX_DMA_CONFIG \
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{ \
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.Instance = SPI2_RX_DMA_INSTANCE, \
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.channel = SPI2_RX_DMA_CHANNEL, \
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.clock = SPI2_RX_DMA_CLOCK, \
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.trigger_select = SPI2_RX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI2_SPRI, \
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.irq_config = \
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{ \
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.irq_num = SPI2_RX_DMA_IRQn, \
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.irq_prio = SPI2_RX_DMA_INT_PRIO, \
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.int_src = SPI2_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI2_RX_DMA_CONFIG */
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#endif /* BSP_SPI2_RX_USING_DMA */
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#ifdef BSP_USING_SPI3
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#ifndef SPI3_BUS_CONFIG
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#define SPI3_BUS_CONFIG \
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{ \
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.Instance = CM_SPI3, \
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.bus_name = "spi3", \
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.clock = FCG1_PERIPH_SPI3, \
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}
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#endif /* SPI3_BUS_CONFIG */
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#endif /* BSP_USING_SPI3 */
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#ifdef BSP_SPI3_TX_USING_DMA
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#ifndef SPI3_TX_DMA_CONFIG
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#define SPI3_TX_DMA_CONFIG \
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{ \
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.Instance = SPI3_TX_DMA_INSTANCE, \
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.channel = SPI3_TX_DMA_CHANNEL, \
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.clock = SPI3_TX_DMA_CLOCK, \
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.trigger_select = SPI3_TX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI3_SPTI, \
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.irq_config = \
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{ \
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.irq_num = SPI3_TX_DMA_IRQn, \
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.irq_prio = SPI3_TX_DMA_INT_PRIO, \
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.int_src = SPI3_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI3_TX_DMA_CONFIG */
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#endif /* BSP_SPI3_TX_USING_DMA */
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#ifdef BSP_SPI3_RX_USING_DMA
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#ifndef SPI3_RX_DMA_CONFIG
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#define SPI3_RX_DMA_CONFIG \
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{ \
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.Instance = SPI3_RX_DMA_INSTANCE, \
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.channel = SPI3_RX_DMA_CHANNEL, \
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.clock = SPI3_RX_DMA_CLOCK, \
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.trigger_select = SPI3_RX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI3_SPRI, \
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.irq_config = \
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{ \
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.irq_num = SPI3_RX_DMA_IRQn, \
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.irq_prio = SPI3_RX_DMA_INT_PRIO, \
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.int_src = SPI3_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI3_RX_DMA_CONFIG */
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#endif /* BSP_SPI3_RX_USING_DMA */
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#ifdef BSP_USING_SPI4
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#ifndef SPI4_BUS_CONFIG
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#define SPI4_BUS_CONFIG \
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{ \
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.Instance = CM_SPI4, \
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.bus_name = "spi4", \
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.clock = FCG1_PERIPH_SPI4, \
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}
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#endif /* SPI4_BUS_CONFIG */
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#endif /* BSP_USING_SPI4 */
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#ifdef BSP_SPI4_TX_USING_DMA
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#ifndef SPI4_TX_DMA_CONFIG
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#define SPI4_TX_DMA_CONFIG \
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{ \
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.Instance = SPI4_TX_DMA_INSTANCE, \
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.channel = SPI4_TX_DMA_CHANNEL, \
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.clock = SPI4_TX_DMA_CLOCK, \
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.trigger_select = SPI4_TX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI4_SPTI, \
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.irq_config = \
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{ \
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.irq_num = SPI4_TX_DMA_IRQn, \
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.irq_prio = SPI4_TX_DMA_INT_PRIO, \
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.int_src = SPI4_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI4_TX_DMA_CONFIG */
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#endif /* BSP_SPI4_TX_USING_DMA */
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#ifdef BSP_SPI4_RX_USING_DMA
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#ifndef SPI4_RX_DMA_CONFIG
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#define SPI4_RX_DMA_CONFIG \
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{ \
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.Instance = SPI4_RX_DMA_INSTANCE, \
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.channel = SPI4_RX_DMA_CHANNEL, \
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.clock = SPI4_RX_DMA_CLOCK, \
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.trigger_select = SPI4_RX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI4_SPRI, \
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.irq_config = \
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{ \
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.irq_num = SPI4_RX_DMA_IRQn, \
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.irq_prio = SPI4_RX_DMA_INT_PRIO, \
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.int_src = SPI4_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI4_RX_DMA_CONFIG */
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#endif /* BSP_SPI4_RX_USING_DMA */
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#ifdef BSP_USING_SPI5
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#ifndef SPI5_BUS_CONFIG
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#define SPI5_BUS_CONFIG \
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{ \
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.Instance = CM_SPI5, \
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.bus_name = "spi5", \
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.clock = FCG1_PERIPH_SPI5, \
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}
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#endif /* SPI5_BUS_CONFIG */
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#endif /* BSP_USING_SPI5 */
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#ifdef BSP_SPI5_TX_USING_DMA
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#ifndef SPI5_TX_DMA_CONFIG
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#define SPI5_TX_DMA_CONFIG \
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{ \
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.Instance = SPI5_TX_DMA_INSTANCE, \
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.channel = SPI5_TX_DMA_CHANNEL, \
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.clock = SPI5_TX_DMA_CLOCK, \
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.trigger_select = SPI5_TX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI5_SPTI, \
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.irq_config = \
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{ \
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.irq_num = SPI5_TX_DMA_IRQn, \
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.irq_prio = SPI5_TX_DMA_INT_PRIO, \
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.int_src = SPI5_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI5_TX_DMA_CONFIG */
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#endif /* BSP_SPI5_TX_USING_DMA */
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#ifdef BSP_SPI5_RX_USING_DMA
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#ifndef SPI5_RX_DMA_CONFIG
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#define SPI5_RX_DMA_CONFIG \
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{ \
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.Instance = SPI5_RX_DMA_INSTANCE, \
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.channel = SPI5_RX_DMA_CHANNEL, \
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.clock = SPI5_RX_DMA_CLOCK, \
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.trigger_select = SPI5_RX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI5_SPRI, \
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.irq_config = \
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{ \
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.irq_num = SPI5_RX_DMA_IRQn, \
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.irq_prio = SPI5_RX_DMA_INT_PRIO, \
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.int_src = SPI5_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI5_RX_DMA_CONFIG */
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#endif /* BSP_SPI5_RX_USING_DMA */
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#ifdef BSP_USING_SPI6
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#ifndef SPI6_BUS_CONFIG
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#define SPI6_BUS_CONFIG \
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{ \
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.Instance = CM_SPI6, \
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.bus_name = "spi6", \
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.clock = FCG1_PERIPH_SPI6, \
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}
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#endif /* SPI6_BUS_CONFIG */
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#endif /* BSP_USING_SPI6 */
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#ifdef BSP_SPI6_TX_USING_DMA
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#ifndef SPI6_TX_DMA_CONFIG
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#define SPI6_TX_DMA_CONFIG \
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{ \
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.Instance = SPI6_TX_DMA_INSTANCE, \
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.channel = SPI6_TX_DMA_CHANNEL, \
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.clock = SPI6_TX_DMA_CLOCK, \
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.trigger_select = SPI6_TX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI6_SPTI, \
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.irq_config = \
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{ \
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.irq_num = SPI6_TX_DMA_IRQn, \
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.irq_prio = SPI6_TX_DMA_INT_PRIO, \
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.int_src = SPI6_TX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI6_TX_DMA_CONFIG */
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#endif /* BSP_SPI6_TX_USING_DMA */
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#ifdef BSP_SPI6_RX_USING_DMA
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#ifndef SPI6_RX_DMA_CONFIG
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#define SPI6_RX_DMA_CONFIG \
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{ \
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.Instance = SPI6_RX_DMA_INSTANCE, \
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.channel = SPI6_RX_DMA_CHANNEL, \
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.clock = SPI6_RX_DMA_CLOCK, \
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.trigger_select = SPI6_RX_DMA_TRIG_SELECT, \
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.trigger_event = EVT_SRC_SPI6_SPRI, \
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.irq_config = \
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{ \
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.irq_num = SPI6_RX_DMA_IRQn, \
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.irq_prio = SPI6_RX_DMA_INT_PRIO, \
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.int_src = SPI6_RX_DMA_INT_SRC, \
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} \
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}
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#endif /* SPI6_RX_DMA_CONFIG */
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#endif /* BSP_SPI6_RX_USING_DMA */
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#ifdef __cplusplus
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}
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#endif
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#endif /*__SPI_CONFIG_H__ */
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