304 lines
7.8 KiB
C
304 lines
7.8 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fpcie.h
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* Date: 2022-02-10 14:55:11
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* LastEditTime: 2022-02-18 08:59:37
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* Description: This files is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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#ifndef DRIVERS_FPCIE_H
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#define DRIVERS_FPCIE_H
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes ******************************/
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/***************************** Include Files *********************************/
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#include "ftypes.h"
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#include "fassert.h"
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#include "fpcie_dma.h"
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#include "fparameters.h"
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#ifdef __aarch64__
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#define CONFIG_SYS_PCI_64BIT 1
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#endif
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#ifdef CONFIG_SYS_PCI_64BIT
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typedef u64 pci_addr_t;
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typedef u64 pci_size_t;
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#else
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typedef u32 pci_addr_t;
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typedef u32 pci_size_t;
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#endif
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typedef boolean bool;
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#define true TRUE
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#define false FALSE
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/* Access sizes for PCI reads and writes */
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enum pci_size_t
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{
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PCI_SIZE_8,
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PCI_SIZE_16,
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PCI_SIZE_32,
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};
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FPCIE_ERR_INVALID_PARAM FT_CODE_ERR(ErrModBsp, ErrPcie, 0x1u)
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#define FPCIE_ERR_OUTOF_BUS FT_CODE_ERR(ErrModBsp, ErrPcie, 0x2u)
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#define FPCIE_ERR_CONFIG_WRITE FT_CODE_ERR(ErrModBsp, ErrPcie, 0x3u)
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#define FPCIE_ERR_TYPE0 FT_CODE_ERR(ErrModBsp, ErrPcie, 0x4u)
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#define FPCIE_ERR_TIMEOUT FT_CODE_ERR(ErrModBsp, ErrPcie, 0x5u)
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#define FPCIE_NEED_SKIP FT_CODE_ERR(ErrModBsp, ErrPcie, 0x6u)
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#define FPCIE_NOT_FOUND FT_CODE_ERR(ErrModBsp, ErrPcie, 0x7u)
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#define FPCIE_REGION_MEM 0x00000000 /* PCI memory space */
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#define FPCIE_REGION_IO 0x00000001 /* PCI IO space */
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#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
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#define FPCIE_BAR_0 0
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#define FPCIE_BAR_1 1
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#define FPCIE_BAR_2 2
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#define FPCIE_BAR_3 3
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#define FPCIE_BAR_4 4
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#define FPCIE_BAR_5 5
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/* PCI-E Unit controller selection */
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#define FPCIE_PEU0_C0 0 /* pcie 0 0号控制器 */
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#define FPCIE_PEU0_C1 1 /* pcie 0 1号控制器 */
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#define FPCIE_PEU0_C2 2 /* pcie 0 2号控制器 */
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#define FPCIE_PEU1_C0 3 /* pcie 1 0号控制器 */
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#define FPCIE_PEU1_C1 4 /* pcie 1 1号控制器 */
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#define FPCIE_PEU1_C2 5 /* pcie 1 2号控制器 */
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#define FPCIE_REGION_EXIST_FLG 1
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/** @name Callback identifiers
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*
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* These constants are used as parameters to FPcieMiscSetHandler()
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* @{
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*/
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#define FPCIE_HANDLER_DMASEND 1U
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#define FPCIE_HANDLER_DMARECV 2U
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#define FPCIE_HANDLER_DMASEND_ERROR 3U
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#define FPCIE_HANDLER_DMARECV_ERROR 4U
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/*@}*/
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typedef void (*FPcieIrqCallBack)(void *args);
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#if defined(__aarch64__)
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typedef u64 FPcieAddr;
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typedef u64 FPcieSize;
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typedef u64 FPciePhysAddr;
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#else
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typedef u32 FPcieAddr;
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typedef u32 FPcieSize;
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typedef u32 FPciePhysAddr;
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#endif
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typedef struct
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{
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u16 vender_id ;
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u16 device_id ;
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u32 bus_num ;
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u32 dev_num ;
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u32 fun_num ;
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u32 class_code ;
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} FPcieSearchFunNode;
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typedef struct
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{
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void (*IntxCallBack)(void *args) ;
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void *args ;
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s32 bdf ;
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} FPcieIntxFun;
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struct FPcieRegion
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{
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FPcieAddr bus_start; /* Start on the bus */
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FPciePhysAddr phys_start; /* Start in physical address space */
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FPcieSize size; /* Size */
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unsigned long flags; /* Resource flags */
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FPcieAddr bus_lower;
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u32 exist_flg; /* exist flg */
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};
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typedef struct
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{
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u16 vendor, device;
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} FpcieId;
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typedef struct
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{
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u32 instance_id; /* Id of device*/
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u32 irq_num; /* Irq number */
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uintptr_t ecam; /* The Memory way */
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uintptr_t peu0_config_address;
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uintptr_t peu1_config_address;
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uintptr_t control_c0_address; //0x29900000
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uintptr_t control_c1_address; //0x29910000
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uintptr_t control_c2_address;
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uintptr_t control_c3_address;
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uintptr_t control_c4_address;
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uintptr_t control_c5_address;
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#ifdef FT_PCI_INTX_EOI
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uintptr_t intx_peux_stat_address[FT_PCI_INTX_SATA_NUM] ;
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uintptr_t intx_control_eux_cx_address[FT_PCI_INTX_CONTROL_NUM] ;
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#endif
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u32 io_base_addr;
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u32 io_size ;
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u32 npmem_base_addr;
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u32 npmem_size;
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u64 pmem_base_addr; /* Prefetchable memory */
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u64 pmem_size;
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u8 inta_irq_num ;
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u8 intb_irq_num ;
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u8 intc_irq_num ;
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u8 intd_irq_num ;
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u8 need_skip ;
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} FPcieConfig;
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typedef struct
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{
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u32 is_ready; /* Device is ininitialized and ready*/
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FPcieConfig config;
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struct FPcieRegion mem;
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struct FPcieRegion mem_prefetch;
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struct FPcieRegion mem_io;
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s32 bus_max; /* 当前最大bus num */
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FPcieIrqCallBack fpcie_dma_rx_cb;
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void *dma_rx_args;
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FPcieIrqCallBack fpcie_dma_tx_cb;
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void *dma_tx_args;
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FPcieIrqCallBack fpcie_dma_rx_error_cb;
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void *dma_rx_error_args;
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FPcieIrqCallBack fpcie_dma_tx_error_cb;
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void *dma_tx_error_args;
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FPcieIntxFun inta_fun[128]; //假设最高支持128个pcie 节点
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FPcieIntxFun intb_fun[128];
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FPcieIntxFun intc_fun[128];
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FPcieIntxFun intd_fun[128];
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s32 scaned_bdf_array[128];
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s32 scaned_bdf_count;
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u32 is_scaned; /* Device is ininitialized and ready*/
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} FPcie;
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FPcieConfig *FPcieLookupConfig(u32 instance_id);
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FError FPcieCfgInitialize(FPcie *instance_p, FPcieConfig *config_p);
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/* dma */
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FError FPcieDmaDescSet(uintptr axi_addr,
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uintptr pcie_addr,
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u32 length,
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struct FPcieDmaDescriptor *desc,
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struct FPcieDmaDescriptor *next_desc);
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void FPcieDmaRead(uintptr cintrol_address, struct FPcieDmaDescriptor *desc);
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void FPcieDmaWrite(uintptr cintrol_address, struct FPcieDmaDescriptor *desc);
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FError FPcieDmaPollDone(struct FPcieDmaDescriptor *desc, u32 wait_cnt);
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/* Intx Interrupt */
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void FPcieIntxIrqHandler(s32 vector, void *args) ;
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FError FPcieIntxRegiterIrqHandler(FPcie *instance_p,
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u32 bdf,
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FPcieIntxFun *intx_fun_p) ;
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void FPcieMiscIrqDisable(FPcie *instance_p, fsize_t peu_num) ;
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struct FPcieBus
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{
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s32 ChildN[32];
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u8 ChildCount;
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} ;
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typedef enum
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{
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HEADER = 0,
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PCIE_CAP = 1,
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PCIE_ECAP = 2
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} BITFIELD_REGISTER_TYPE;
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const char *FPcieClassStr(u8 class);
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void FPcieAutoRegionAlign(struct FPcieRegion *res, pci_size_t size);
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int FPcieAutoRegionAllocate(struct FPcieRegion *res, pci_size_t size,
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pci_addr_t *bar, bool supports_64bit);
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void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
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struct FPcieRegion *mem,
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struct FPcieRegion *prefetch, struct FPcieRegion *io,
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bool enum_only);
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void FPcieAutoPrescanSetupBridge(FPcie *instance_p, u32 bdf, int sub_bus);
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void FPcieAutoPostscanSetupBridge(FPcie *instance_p, u32 bdf, int sub_bus);
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int FPcieHoseProbeBus(FPcie *instance_p, u32 bdf);
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int FPcieAutoConfigDevice(FPcie *instance_p, u32 bdf);
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FError FPcieBindBusDevices(FPcie *instance_p, u32 bus_num, u32 parent_bdf, struct FPcieBus *bus);
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FError FPcieScanBus(FPcie *instance_p, u32 bus_num, u32 parent_bdf);
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#ifdef __cplusplus
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}
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#endif
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#endif // !
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