330 lines
13 KiB
C
330 lines
13 KiB
C
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////////////////////////////////////////////////////////////////////////////////
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/// @file hal_rcc.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RCC
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/// FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __HAL_RCC_H
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#define __HAL_RCC_H
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// Files includes
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#include "types.h"
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#include "reg_common.h"
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#include "mm32_reg.h"
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////////////////////////////////////////////////////////////////////////////////
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/// @addtogroup MM32_Hardware_Abstract_Layer
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup RCC_HAL
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/// @brief RCC HAL modules
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup RCC_Exported_Types
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup RCC_Exported_Constants
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/// @{
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup RCC_Exported_Enumeration
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @brief HSE configuration
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_HSE_OFF = 0, // HSE OFF
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RCC_HSE_ON = RCC_CR_HSEON, // HSE ON
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RCC_HSE_Bypass = RCC_CR_HSEBYP // HSE Bypass
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} RCCHSE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Used for flags
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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CR_REG_INDEX = 1, //
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BDCR_REG_INDEX = 2, //
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CSR_REG_INDEX = 3, //
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RCC_FLAG_MASK = 0x1FU //
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} RCC_RegisterFlag_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RCC Flag
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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// Flags in the CR register
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RCC_FLAG_HSIRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)), ///< Internal High Speed clock ready flag
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RCC_FLAG_HSERDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)), ///< External High Speed clock ready flag
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RCC_FLAG_PLLRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)), ///< PLL clock ready flag
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// Flags in the CSR register
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RCC_FLAG_LSIRDY = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)), ///< Internal Low Speed oscillator Ready
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RCC_FLAG_PINRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)), ///< PIN reset flag
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RCC_FLAG_PORRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)), ///< POR/PDR reset flag
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RCC_FLAG_SFTRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)), ///< Software Reset flag
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RCC_FLAG_IWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)), ///< Independent Watchdog reset flag
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RCC_FLAG_WWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)), ///< Window watchdog reset flag
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// Flags in the BDCR register
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RCC_FLAG_LSERDY = ((u8)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) ///< External Low Speed oscillator Ready
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} RCC_FLAG_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief System clock source
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_HSI = 0, // Set HSI as systemCLOCK
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RCC_HSE = 1, // Set HSE as systemCLOCK
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RCC_PLL = 2, // Set PLL as systemCLOCK
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RCC_LSI = 3 // Set LSI as systemCLOCK
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} SYSCLK_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief PLL entry clock source
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_HSI_Div4 = 0,
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RCC_HSI_Div = 0,
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RCC_HSE_Div1 = RCC_PLLCFGR_PLLSRC,
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RCC_HSE_Div2 = (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC),
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} RCC_PLLSource_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief PLL multiplication factor
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_PLLMul_2 = 0x00000000U,
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RCC_PLLMul_3 = 0x00040000U,
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RCC_PLLMul_4 = 0x00080000U,
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RCC_PLLMul_5 = 0x000C0000U,
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RCC_PLLMul_6 = 0x00100000U,
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RCC_PLLMul_7 = 0x00140000U,
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RCC_PLLMul_8 = 0x00180000U,
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RCC_PLLMul_9 = 0x001C0000U,
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RCC_PLLMul_10 = 0x00200000U,
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RCC_PLLMul_11 = 0x00240000U,
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RCC_PLLMul_12 = 0x00280000U,
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RCC_PLLMul_13 = 0x002C0000U,
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RCC_PLLMul_14 = 0x00300000U,
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RCC_PLLMul_15 = 0x00340000U,
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RCC_PLLMul_16 = 0x00380000U
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} RCC_PLLMul_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief AHB clock source
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_SYSCLK_Div1 = RCC_CFGR_HPRE_DIV1,
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RCC_SYSCLK_Div2 = RCC_CFGR_HPRE_DIV2,
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RCC_SYSCLK_Div4 = RCC_CFGR_HPRE_DIV4,
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RCC_SYSCLK_Div8 = RCC_CFGR_HPRE_DIV8,
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RCC_SYSCLK_Div16 = RCC_CFGR_HPRE_DIV16,
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RCC_SYSCLK_Div64 = RCC_CFGR_HPRE_DIV64,
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RCC_SYSCLK_Div128 = RCC_CFGR_HPRE_DIV128,
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RCC_SYSCLK_Div256 = RCC_CFGR_HPRE_DIV256,
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RCC_SYSCLK_Div512 = RCC_CFGR_HPRE_DIV512
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} RCC_AHB_CLK_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief APB1 and APB2clock source
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_HCLK_Div1 = RCC_CFGR_PPRE1_DIV1,
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RCC_HCLK_Div2 = RCC_CFGR_PPRE1_DIV2,
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RCC_HCLK_Div4 = RCC_CFGR_PPRE1_DIV4,
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RCC_HCLK_Div8 = RCC_CFGR_PPRE1_DIV8,
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RCC_HCLK_Div16 = RCC_CFGR_PPRE1_DIV16
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} RCC_APB1_APB2_CLK_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief USB Device clock source
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_USBCLKSource_PLLCLK_Div1 = 0,
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RCC_USBCLKSource_PLLCLK_Div2 = 1,
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RCC_USBCLKSource_PLLCLK_Div3 = 2,
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RCC_USBCLKSource_PLLCLK_Div4 = 3
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} RCC_USBCLKSOURCE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief ADC clock source
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_PCLK2_Div2 = (0x00000000),
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RCC_PCLK2_Div4 = (0x00004000),
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RCC_PCLK2_Div6 = (0x00008000),
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RCC_PCLK2_Div8 = (0x0000C000)
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} RCC_ADCCLKSOURCE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief LSE configuration
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_LSE_OFF = 0, // LSE OFF
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RCC_LSE_ON = RCC_BDCR_LSEON, // LSE ON
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RCC_LSE_Bypass = RCC_BDCR_LSEBYP // LSE Bypass
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} RCC_LSE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RTC clock source
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_RTCCLKSource_LSE = RCC_BDCR_RTCSEL_LSE,
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RCC_RTCCLKSource_LSI = RCC_BDCR_RTCSEL_LSI,
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RCC_RTCCLKSource_HSE_Div128 = RCC_BDCR_RTCSEL_HSE
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} RCC_RTCCLKSOURCE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Clock source to output on MCO pin
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_MCO_NoClock = RCC_CFGR_MCO_NOCLOCK,
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RCC_MCO_LSI = RCC_CFGR_MCO_LSI,
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RCC_MCO_LSE = RCC_CFGR_MCO_LSE,
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RCC_MCO_SYSCLK = RCC_CFGR_MCO_SYSCLK,
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RCC_MCO_HSI = RCC_CFGR_MCO_HSI,
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RCC_MCO_HSE = RCC_CFGR_MCO_HSE,
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RCC_MCO_PLLCLK_Div2 = RCC_CFGR_MCO_PLL
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} RCC_MCO_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RCC Interrupt source
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////////////////////////////////////////////////////////////////////////////////
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typedef enum {
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RCC_IT_LSIRDY = RCC_CIR_LSIRDYF,
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RCC_IT_LSERDY = RCC_CIR_LSERDYF,
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RCC_IT_HSIRDY = RCC_CIR_HSIRDYF,
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RCC_IT_HSERDY = RCC_CIR_HSERDYF,
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RCC_IT_PLLRDY = RCC_CIR_PLLRDYF,
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RCC_IT_CSS = RCC_CIR_CSSF
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} RCC_IT_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief RCC clock frequency type definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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u32 SYSCLK_Frequency; ///< returns SYSCLK clock frequency.
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u32 HCLK_Frequency; ///< returns hclk clock frequency.
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u32 PCLK1_Frequency; ///< returns PCLK1 clock frequency.
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u32 PCLK2_Frequency; ///< returns PCLK2 clock frequency.
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u32 ADCCLK_Frequency; ///< returns ADCCLK clock frequency.
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} RCC_ClocksTypeDef;
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup RCC_Exported_Variables
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/// @{
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#ifdef _HAL_RCC_C_
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#define GLOBAL
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#else
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#define GLOBAL extern
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#endif
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#undef GLOBAL
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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/// @defgroup RCC_Exported_Functions
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/// @{
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void RCC_DeInit(void);
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void RCC_HSEConfig(RCCHSE_TypeDef state);
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void RCC_HSICmd(FunctionalState state);
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void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_src);
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void RCC_PLLDMDNConfig(u32 plldn, u32 plldm);
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void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul);
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void RCC_PLLCmd(FunctionalState state);
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void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk);
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void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk);
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void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk);
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void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src);
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void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2);
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void RCC_LSICmd(FunctionalState state);
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void RCC_RTCCLKCmd(FunctionalState state);
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void RCC_LSEConfig(RCC_LSE_TypeDef state);
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void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src);
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void RCC_BackupResetCmd(FunctionalState state);
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void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk);
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void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state);
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void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state);
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void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state);
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void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state);
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void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state);
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void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state);
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void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state);
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void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state);
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void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state);
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void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state);
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void RCC_ClockSecuritySystemCmd(FunctionalState state);
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void RCC_MCOConfig(RCC_MCO_TypeDef mco_src);
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void RCC_ClearFlag(void);
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void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state);
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void RCC_ClearITPendingBit(u8 it);
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u8 RCC_GetSYSCLKSource(void);
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u32 RCC_GetSysClockFreq(void);
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u32 RCC_GetHCLKFreq(void);
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u32 RCC_GetPCLK1Freq(void);
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u32 RCC_GetPCLK2Freq(void);
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FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag);
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ErrorStatus RCC_WaitForHSEStartUp(void);
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ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag);
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ITStatus RCC_GetITStatus(RCC_IT_TypeDef it);
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////////////////////////////////////////////////////////////////////////////////
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// Extended function interface
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////////////////////////////////////////////////////////////////////////////////
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//ErrorStatus exRCC_Init(RCCInitStruct_TypeDef* para);
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void exRCC_SystickDisable(void);
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void exRCC_SystickEnable(u32 sys_tick_period);
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void exRCC_APB1PeriphReset(u32 apb1_periph);
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void exRCC_APB2PeriphReset(u32 apb2_periph);
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void exRCC_BackupReset(void);
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void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state);
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void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state);
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/// @}
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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#endif // __HAL_RCC_H
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////////////////////////////////////////////////////////////////////////////////
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