220 lines
9.3 KiB
C
220 lines
9.3 KiB
C
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/*
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* Copyright (c) 2022 OpenLuat & AirM2M
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AIR105_DMA_H
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#define __AIR105_DMA_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "air105.h"
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typedef struct
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{
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uint32_t DMA_Peripheral;
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uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
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uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
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uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
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This parameter can be a value of @ref DMA_data_transfer_direction */
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uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
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This parameter can be a value of @ref DMA_incremented_mode */
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uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
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This parameter can be a value of @ref DMA_incremented_mode */
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uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data item width.
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This parameter can be a value of @ref DMA_data_size */
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uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data item width.
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This parameter can be a value of @ref DMA_data_size */
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uint32_t DMA_PeripheralBurstSize; /*!< Specifies the Peripheral Number of data items during per burst transaction.
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read or write from the Peripheral every time a burst transaction request
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This parameter can be a value of @ref DMA_burst_size */
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uint32_t DMA_MemoryBurstSize; /*!< Specifies the Memory Number of data items during per burst transaction.
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read or write from the Memory every time a burst transaction request
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This parameter can be a value of @ref DMA_burst_size */
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uint32_t DMA_PeripheralHandShake; /*!< Specifies the HandShake to control the DMA transacation.
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This parameter can be a value of @ref DMA_peripheral_handshake */
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uint32_t DMA_BlockSize; /*!< Specifies the Total Number of data items during the transaction. */
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uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
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This parameter can be a value of @ref DMA_priority_level */
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}DMA_InitTypeDef;
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/**
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* DMA多块传输内存表
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*
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*/
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typedef struct _lli
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{
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uint32_t SAR;
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uint32_t DAR;
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uint32_t LLP;
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uint32_t CTL_L;
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uint32_t CTL_H;
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uint32_t DSTAT;
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}LLI;
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/**多块传输模式
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* @}
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*/
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#define Multi_Block_MODE01 (uint8_t)0x00 /*Single-block or last transfer of multi-block*/
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#define Multi_Block_MODE02 (uint8_t)0x01 /*Auto-reload multi-block transfer with contiguous SAR*/
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#define Multi_Block_MODE03 (uint8_t)0x02 /*Auto-reload multi-block transfer with contiguous DAR*/
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#define Multi_Block_MODE04 (uint8_t)0x03 /*Auto-reload multi-block transfer*/
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#define Multi_Block_MODE05 (uint8_t)0x04 /*Single-block or last transfer of multi-block*/
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#define Multi_Block_MODE06 (uint8_t)0x05 /*Linked list multi-block transfer with contiguous SAR*/
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#define Multi_Block_MODE07 (uint8_t)0x06 /*Linked list multi-block transfer with auto-reload SAR*/
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#define Multi_Block_MODE08 (uint8_t)0x07 /*Linked list multi-block transfer with contiguous DAR*/
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#define Multi_Block_MODE09 (uint8_t)0x08 /*Linked list multi-block transfer with auto-reload DAR*/
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#define Multi_Block_MODE10 (uint8_t)0x09 /*Linked list multi-block transfer*/
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/** @defgroup DMA_data_transfer_direction
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* @{
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*/
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#define DMA_DIR_Memory_To_Memory ((uint32_t)0x0000)
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#define DMA_DIR_Memory_To_Peripheral ((uint32_t)0x0001)
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#define DMA_DIR_Peripheral_To_Memory ((uint32_t)0x0002)
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/**
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* @}
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*/
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/** @defgroup DMA_incremented_mode
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* @{
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*/
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#define DMA_Inc_Increment ((uint32_t)0x00000000)
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#define DMA_Inc_Decrement ((uint32_t)0x00000001)
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#define DMA_Inc_Nochange ((uint32_t)0x00000002)
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#define IS_DMA_INC_STATE(STATE) (((STATE) == DMA_Inc_Increment) || \
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((STATE) == DMA_Inc_Decrement) || \
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((STATE) == DMA_Inc_Nochange))
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/**
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* @}
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*/
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/** @defgroup DMA_data_size
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* @{
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*/
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#define DMA_DataSize_Byte ((uint32_t)0x0000)
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#define DMA_DataSize_HalfWord ((uint32_t)0x0001)
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#define DMA_DataSize_Word ((uint32_t)0x0002)
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#define IS_DMA_DATA_SIZE(SIZE) (((SIZE) == DMA_DataSize_Byte) || \
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((SIZE) == DMA_DataSize_HalfWord) || \
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((SIZE) == DMA_DataSize_Word))
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/**
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* @}
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*/
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/** @defgroup DMA_burst_size
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* @{
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*/
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#define DMA_BurstSize_1 ((uint32_t)0x00)
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#define DMA_BurstSize_4 ((uint32_t)0x01)
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#define DMA_BurstSize_8 ((uint32_t)0x02)
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#define DMA_BurstSize_16 ((uint32_t)0x03)
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#define DMA_BurstSize_32 ((uint32_t)0x04)
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/**
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* @}
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*/
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/** @defgroup DMA_peripheral_handshake
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* @{
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*/
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#define DMA_PeripheralHandShake_Hardware ((uint32_t)0x0000)
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#define DMA_PeripheralHandShake_Software ((uint32_t)0x0001)
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/**
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* @}
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*/
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/** @defgroup DMA_Priority
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* @{
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*/
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#define DMA_Priority_0 ((uint32_t)0x00000000)
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#define DMA_Priority_1 ((uint32_t)0x00000020)
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#define DMA_Priority_2 ((uint32_t)0x00000040)
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#define DMA_Priority_3 ((uint32_t)0x00000060)
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#define DMA_Priority_4 ((uint32_t)0x00000080)
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#define DMA_Priority_5 ((uint32_t)0x000000A0)
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#define DMA_Priority_6 ((uint32_t)0x000000C0)
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/**
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* @}
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*/
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/** @defgroup DMA_IT
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* @{
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*/
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#define DMA_IT_BlockTransferComplete ((uint32_t)0x01)
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#define DMA_IT_DestinationTransactionComplete ((uint32_t)0x02)
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#define DMA_IT_Error ((uint32_t)0x04)
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#define DMA_IT_SourceTransactionComplete ((uint32_t)0x08)
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#define DMA_IT_DMATransferComplete ((uint32_t)0x10)
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/**
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* @}
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*/
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void DMA_Init(DMA_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct);
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void DMA_ChannelCmd(DMA_TypeDef* DMA_Channelx, FunctionalState NewState);
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void DMA_Cmd(FunctionalState NewState);
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void DMA_ChannelConfig(DMA_TypeDef* DMA_Channelx, uint32_t DMA_Peripheral, uint32_t DMA_DIR);
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void DMA_SetSRCAddress(DMA_TypeDef* DMA_Channelx, uint32_t Address);
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void DMA_SetDSRAddress(DMA_TypeDef* DMA_Channelx, uint32_t Address);
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void DMA_ITConfig(DMA_TypeDef* DMA_Channelx, uint32_t DMA_IT, FunctionalState NewState);
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FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
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void DMA_ClearFlag(uint32_t DMA_FLAG);
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FunctionalState DMA_IsChannelEnabled(DMA_TypeDef* DMA_Channelx);
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ITStatus DMA_GetITStatus(DMA_TypeDef* DMA_Channelx,uint32_t DMA_IT);
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FlagStatus DMA_GetRawStatus(DMA_TypeDef* DMA_Channelx,uint32_t DMA_IT);
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void DMA_ClearITPendingBit(DMA_TypeDef* DMA_Channelx,uint32_t DMA_IT);
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void DMA_MultiBlockInit(DMA_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct ,\
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LLI *first_lli,uint8_t Multi_Block_Mode);
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void DMA_InitLLI(DMA_TypeDef* DMA_Channelx,LLI *lli,LLI *next_lli,
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void *src_addr,void *dest_addr,uint16_t btsize);
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uint32_t DMA_GetTransferNum(DMA_TypeDef* DMA_Channelx, uint32_t first_adr);
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#ifdef __cplusplus
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}
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#endif
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#endif
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/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/
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