204 lines
8.2 KiB
C
204 lines
8.2 KiB
C
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/*
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* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-11-16 Dystopia the first version
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*/
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#include "common.h"
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CSL_BootcfgRegs * gp_bootcfg_regs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
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CSL_CgemRegs * gp_cgem_regs = (CSL_CgemRegs *)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;
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CSL_TmrPlusRegs * gp_timer_regs[9] = {
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(CSL_TmrPlusRegs *)CSL_TIMER_0_REGS,
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(CSL_TmrPlusRegs *)CSL_TIMER_1_REGS,
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(CSL_TmrPlusRegs *)CSL_TIMER_2_REGS,
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(CSL_TmrPlusRegs *)CSL_TIMER_3_REGS,
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(CSL_TmrPlusRegs *)CSL_TIMER_4_REGS,
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(CSL_TmrPlusRegs *)CSL_TIMER_5_REGS,
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(CSL_TmrPlusRegs *)CSL_TIMER_6_REGS,
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(CSL_TmrPlusRegs *)CSL_TIMER_7_REGS,
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(CSL_TmrPlusRegs *)(CSL_TIMER_7_REGS+(CSL_TIMER_7_REGS-CSL_TIMER_6_REGS))
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};
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void cpu_interrupt_init(void)
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{
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//clear interrupt and excpetion events
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ICR = IFR;
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ECR = EFR;
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IER = 3; //disable all interrupts
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/* disable event combine */
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gp_cgem_regs->EVTMASK[0] = 0xffffffff;
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gp_cgem_regs->EVTMASK[1] = 0xffffffff;
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gp_cgem_regs->EVTMASK[2] = 0xffffffff;
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gp_cgem_regs->EVTMASK[3] = 0xffffffff;
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/*Clear all CPU events*/
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gp_cgem_regs->EVTCLR[0] = 0xFFFFFFFF;
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gp_cgem_regs->EVTCLR[1] = 0xFFFFFFFF;
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gp_cgem_regs->EVTCLR[2] = 0xFFFFFFFF;
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gp_cgem_regs->EVTCLR[3] = 0xFFFFFFFF;
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/*Interrupt Service Table Pointer to begining of LL2 memory*/
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ISTP = 0x800000;
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}
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void keystone_cpu_init(void)
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{
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/* clear all interrupt flag/status, setup ISTP to begining of LL2 */
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cpu_interrupt_init();
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}
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/*===============================Timer=================================*/
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void reset_timer(int timer_num)
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{
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if(gp_timer_regs[timer_num]->TGCR)
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{
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gp_timer_regs[timer_num]->TGCR = 0;
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gp_timer_regs[timer_num]->TCR= 0;
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}
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}
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void timer64_init(Timer64_Config * tmrCfg)
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{
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reset_timer(tmrCfg->timer_num);
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gp_timer_regs[tmrCfg->timer_num]->CNTLO = 0;
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gp_timer_regs[tmrCfg->timer_num]->CNTHI = 0;
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/*please note, in clock mode, two timer periods generate a clock,
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one timer period output high voltage level, the other timer period
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output low voltage level, so, the timer period should be half to the
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desired output clock period*/
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if(TIMER_PERIODIC_CLOCK == tmrCfg->timerMode)
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{
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tmrCfg->period = tmrCfg->period/2;
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}
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/*the value written into period register is the expected value minus one*/
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gp_timer_regs[tmrCfg->timer_num]->PRDLO = _loll(tmrCfg->period-1);
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gp_timer_regs[tmrCfg->timer_num]->PRDHI = _hill(tmrCfg->period-1);
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if(tmrCfg->reload_period>1)
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{
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gp_timer_regs[tmrCfg->timer_num]->RELLO = _loll(tmrCfg->reload_period-1);
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gp_timer_regs[tmrCfg->timer_num]->RELHI = _hill(tmrCfg->reload_period-1);
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}
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if(TIMER_WATCH_DOG == tmrCfg->timerMode)
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{
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gp_timer_regs[tmrCfg->timer_num]->TGCR =
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/*Select watch-dog mode*/
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(CSL_TMR_TIMMODE_WDT << CSL_TMR_TGCR_TIMMODE_SHIFT)
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/*Remove the timer from reset*/
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| (CSL_TMR_TGCR_TIMLORS_MASK)
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| (CSL_TMR_TGCR_TIMHIRS_MASK);
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}
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else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
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{
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gp_timer_regs[tmrCfg->timer_num]->TGCR = TMR_TGCR_PLUSEN_MASK
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/*for plus featuers, dual 32-bit unchained timer mode should be used*/
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| (CSL_TMR_TIMMODE_DUAL_UNCHAINED << CSL_TMR_TGCR_TIMMODE_SHIFT)
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/*Remove the timer from reset*/
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| (CSL_TMR_TGCR_TIMLORS_MASK);
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//in plus mode, interrupt/event must be enabled manually
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gp_timer_regs[tmrCfg->timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL;
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}
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else
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{
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gp_timer_regs[tmrCfg->timer_num]->TGCR =
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/*Select 64-bit general timer mode*/
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(CSL_TMR_TIMMODE_GPT << CSL_TMR_TGCR_TIMMODE_SHIFT)
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/*Remove the timer from reset*/
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| (CSL_TMR_TGCR_TIMLORS_MASK)
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| (CSL_TMR_TGCR_TIMHIRS_MASK);
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}
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/*make timer stop with emulation*/
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gp_timer_regs[tmrCfg->timer_num]->EMUMGT_CLKSPD = (gp_timer_regs[tmrCfg->timer_num]->EMUMGT_CLKSPD&
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~(CSL_TMR_EMUMGT_CLKSPD_FREE_MASK|CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK));
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if(TIMER_WATCH_DOG == tmrCfg->timerMode)
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{
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/*enable watchdog timer*/
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gp_timer_regs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
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| (CSL_TMR_WDTCR_WDKEY_CMD1 << CSL_TMR_WDTCR_WDKEY_SHIFT);
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gp_timer_regs[tmrCfg->timer_num]->TCR =
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(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
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| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
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/*The timer is enabled continuously*/
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| (CSL_TMR_ENAMODE_CONT << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
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| ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
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/*select pulse mode*/
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| (CSL_TMR_CP_PULSE << CSL_TMR_TCR_CP_LO_SHIFT)
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| (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
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| (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
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| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
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/*active watchdog timer*/
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gp_timer_regs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
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| (CSL_TMR_WDTCR_WDKEY_CMD2 << CSL_TMR_WDTCR_WDKEY_SHIFT);
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}
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else if(TIMER_ONE_SHOT_PULSE == tmrCfg->timerMode)
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{
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gp_timer_regs[tmrCfg->timer_num]->TCR =
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(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
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| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
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/*The timer is enabled one-shot*/
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| (CSL_TMR_ENAMODE_ENABLE << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
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| ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
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/*select pulse mode*/
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| (CSL_TMR_CP_PULSE << CSL_TMR_TCR_CP_LO_SHIFT)
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| (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
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| (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
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| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
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}
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else if(TIMER_PERIODIC_CLOCK == tmrCfg->timerMode)
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{
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gp_timer_regs[tmrCfg->timer_num]->TCR =
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(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
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| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
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/*The timer is enabled continuously*/
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| (CSL_TMR_ENAMODE_CONT << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
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| ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
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/*select clock mode*/
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| (CSL_TMR_CP_CLOCK << CSL_TMR_TCR_CP_LO_SHIFT)
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| (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
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| (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
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| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
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}
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else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
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{
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gp_timer_regs[tmrCfg->timer_num]->TCR =
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(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
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| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
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/*The timer is enabled continuously with period reload*/
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| (CSL_TMR_ENAMODE_CONT_RELOAD << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
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| ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
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/*select clock mode*/
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| (CSL_TMR_CP_CLOCK << CSL_TMR_TCR_CP_LO_SHIFT)
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| (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
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| (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
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| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
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}
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else /*TIMER_PERIODIC_PULSE*/
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{
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gp_timer_regs[tmrCfg->timer_num]->TCR =
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(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
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| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
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/*The timer is enabled continuously*/
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| (CSL_TMR_ENAMODE_CONT << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
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| ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
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/*select clock mode*/
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| (CSL_TMR_CP_PULSE << CSL_TMR_TCR_CP_LO_SHIFT)
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| (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
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| (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
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| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
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}
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}
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