84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
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/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-12-12 Wayne First version
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*
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******************************************************************************/
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#ifndef __DRV_COMMON_H__
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#define __DRV_COMMON_H__
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#include <rtthread.h>
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#include "NuMicro.h"
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#include "interrupt.h"
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#if !defined(USE_MA35D1_SUBM)
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#include "gic.h"
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#include "mmu.h"
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#include "cp15.h"
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#include "gtimer.h"
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#define __REG32(x) (*((volatile unsigned int*)((rt_ubase_t)x)))
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#define GIC_ACK_INTID_MASK 0x000003ff
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#define ARM_GIC_NR_IRQS 256
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#define MAX_HANDLERS ARM_GIC_NR_IRQS
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#define ARM_GIC_MAX_NR 1
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#define GIC_IRQ_START 0
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#define DDR_LIMIT_SIZE 0xC0000000u
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#define UNCACHEABLE 0x40000000u
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#define SSPCC_SET_REALM(IP, REALM) \
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do { \
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rt_kprintf("Set %s realm to %s(%d)\n", #IP, #REALM, REALM); \
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SSPCC_SetRealm(IP, REALM); \
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rt_kprintf("Get %s realm is %d ....%s\n", #IP, SSPCC_GetRealm(IP), (SSPCC_GetRealm(IP)==REALM)?"Success":"Failure"); \
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} while(0)
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#define SSPCC_SET_GPIO_REALM(PORT, PIN, REALM) \
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do { \
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rt_kprintf("Set %s%s realm to %s(%d)\n", #PORT, #PIN, #REALM, REALM); \
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SSPCC_SetRealm_GPIO((uint32_t)PORT, PIN, REALM); \
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rt_kprintf("Get %s%s realm is %d ....%s\n", #PORT, #PIN, SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN), (SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN)==REALM)?"Success":"Failure"); \
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} while(0)
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/* the basic constants needed by gic */
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rt_inline rt_uint32_t platform_get_gic_dist_base(void)
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{
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return GIC_DISTRIBUTOR_BASE;
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}
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rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
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{
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return GIC_INTERFACE_BASE;
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}
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rt_inline rt_uint32_t nu_cpu_dcache_line_size(void)
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{
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rt_uint32_t ctr = 0;
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#if defined(USE_MA35D1_AARCH32)
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asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr));
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#elif defined(USE_MA35D1_AARCH64)
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asm volatile("mrs %0, ctr_el0" : "=r"(ctr));
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#endif
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return 4 << ((ctr >> 16) & 0xF);
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}
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extern void rt_hw_cpu_dcache_clean(void *addr, int size);
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extern void rt_hw_cpu_dcache_clean_inv(void *addr, int size);
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extern void rt_hw_cpu_dcache_invalidate(void *addr, int size);
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#else
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#define UNCACHEABLE 0
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#endif
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void nu_clock_init(void);
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#endif /* __DRV_COMMON_H__ */
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