384 lines
6.9 KiB
C
384 lines
6.9 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-12-20 GuEe-GUI first version
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* 2022-08-24 GuEe-GUI Add OFW support
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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/* support registers access and timer registers in libcpu */
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#include <cpu.h>
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#include <cpuport.h>
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typedef void (*timer_ctrl_handle)(rt_bool_t enable);
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typedef rt_uint64_t (*timer_value_handle)(rt_uint64_t val);
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static volatile rt_uint64_t timer_step;
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static int arm_arch_timer_irq = -1;
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static timer_ctrl_handle arm_arch_timer_ctrl_handle = RT_NULL;
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static timer_value_handle arm_arch_timer_value_handle = RT_NULL;
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/* CTL */
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static void mon_ptimer_ctrl(rt_bool_t enable)
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{
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rt_hw_sysreg_write(CNTPS_CTL, !!enable);
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}
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static void hyp_s_ptimer_ctrl(rt_bool_t enable)
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{
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#if ARCH_ARMV8_EXTENSIONS > 1
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rt_hw_sysreg_write(CNTHPS_CTL, !!enable);
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#endif
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}
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static void hyp_ns_ptimer_ctrl(rt_bool_t enable)
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{
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rt_hw_sysreg_write(CNTHP_CTL, !!enable);
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}
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static void hyp_s_vtimer_ctrl(rt_bool_t enable)
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{
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#if ARCH_ARMV8_EXTENSIONS > 1
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rt_hw_sysreg_write(CNTHVS_CTL, !!enable);
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#endif
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}
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static void hyp_ns_vtimer_ctrl(rt_bool_t enable)
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{
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#if ARCH_ARMV8_EXTENSIONS > 1
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rt_hw_sysreg_write(CNTHV_CTL, !!enable);
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#endif
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}
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static void os_ptimer_ctrl(rt_bool_t enable)
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{
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rt_hw_sysreg_write(CNTP_CTL, !!enable);
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}
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static void os_vtimer_ctrl(rt_bool_t enable)
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{
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rt_hw_sysreg_write(CNTV_CTL, !!enable);
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}
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/* TVAL */
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static rt_uint64_t mon_ptimer_value(rt_uint64_t val)
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{
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if (val)
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{
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rt_hw_sysreg_write(CNTPS_TVAL, val);
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}
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else
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{
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rt_hw_sysreg_read(CNTPS_TVAL, val);
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}
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return val;
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}
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static rt_uint64_t hyp_s_ptimer_value(rt_uint64_t val)
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{
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#if ARCH_ARMV8_EXTENSIONS > 1
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if (val)
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{
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rt_hw_sysreg_write(CNTHPS_TVAL, val);
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}
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else
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{
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rt_hw_sysreg_read(CNTHPS_TVAL, val);
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}
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return val;
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#else
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return 0;
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#endif
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}
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static rt_uint64_t hyp_ns_ptimer_value(rt_uint64_t val)
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{
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if (val)
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{
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rt_hw_sysreg_write(CNTHP_TVAL, val);
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}
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else
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{
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rt_hw_sysreg_read(CNTHP_TVAL, val);
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}
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return val;
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}
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static rt_uint64_t hyp_s_vtimer_value(rt_uint64_t val)
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{
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#if ARCH_ARMV8_EXTENSIONS > 1
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if (val)
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{
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rt_hw_sysreg_write(CNTHVS_TVAL, val);
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}
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else
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{
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rt_hw_sysreg_read(CNTHVS_TVAL, val);
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}
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return val;
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#else
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return 0;
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#endif
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}
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static rt_uint64_t hyp_ns_vtimer_value(rt_uint64_t val)
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{
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#if ARCH_ARMV8_EXTENSIONS > 1
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if (val)
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{
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rt_hw_sysreg_write(CNTHV_TVAL, val);
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}
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else
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{
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rt_hw_sysreg_read(CNTHV_TVAL, val);
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}
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return val;
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#else
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return 0;
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#endif
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}
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static rt_uint64_t os_ptimer_value(rt_uint64_t val)
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{
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if (val)
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{
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rt_hw_sysreg_write(CNTP_TVAL, val);
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}
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else
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{
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rt_hw_sysreg_read(CNTP_TVAL, val);
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}
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return val;
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}
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static rt_uint64_t os_vtimer_value(rt_uint64_t val)
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{
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if (val)
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{
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rt_hw_sysreg_write(CNTV_TVAL, val);
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}
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else
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{
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rt_hw_sysreg_read(CNTV_TVAL, val);
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}
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return val;
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}
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static timer_ctrl_handle ctrl_handle[] =
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{
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mon_ptimer_ctrl,
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hyp_s_ptimer_ctrl,
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hyp_ns_ptimer_ctrl,
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hyp_s_vtimer_ctrl,
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hyp_ns_vtimer_ctrl,
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os_ptimer_ctrl,
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os_vtimer_ctrl,
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};
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static timer_value_handle value_handle[] =
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{
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mon_ptimer_value,
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hyp_s_ptimer_value,
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hyp_ns_ptimer_value,
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hyp_s_vtimer_value,
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hyp_ns_vtimer_value,
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os_ptimer_value,
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os_vtimer_value,
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};
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static rt_err_t arm_arch_timer_local_enable(void)
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{
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rt_err_t ret = RT_EOK;
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if (arm_arch_timer_irq >= 0)
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{
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arm_arch_timer_ctrl_handle(RT_FALSE);
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arm_arch_timer_value_handle(timer_step);
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rt_hw_interrupt_umask(arm_arch_timer_irq);
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arm_arch_timer_ctrl_handle(RT_TRUE);
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}
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else
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{
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ret = -RT_ENOSYS;
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}
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return ret;
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}
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rt_used
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static rt_err_t arm_arch_timer_local_disable(void)
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{
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rt_err_t ret = RT_EOK;
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if (arm_arch_timer_ctrl_handle)
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{
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arm_arch_timer_ctrl_handle(RT_FALSE);
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rt_hw_interrupt_mask(arm_arch_timer_irq);
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}
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else
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{
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ret = -RT_ENOSYS;
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}
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return ret;
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}
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rt_used
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static rt_err_t arm_arch_timer_set_frequency(rt_uint64_t frq)
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{
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rt_err_t ret = RT_EOK;
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#ifdef ARCH_SUPPORT_TEE
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rt_hw_isb();
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rt_hw_sysreg_write(CNTFRQ, frq);
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rt_hw_dsb();
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#else
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ret = -RT_ENOSYS;
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#endif
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return ret;
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}
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rt_used
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static rt_uint64_t arm_arch_timer_get_frequency(void)
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{
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rt_uint64_t frq;
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rt_hw_isb();
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rt_hw_sysreg_read(CNTFRQ, frq);
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rt_hw_isb();
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return frq;
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}
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rt_used
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static rt_err_t arm_arch_timer_set_value(rt_uint64_t val)
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{
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rt_err_t ret = RT_EOK;
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if (arm_arch_timer_value_handle)
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{
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val = arm_arch_timer_value_handle(val);
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}
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else
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{
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ret = -RT_ENOSYS;
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}
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return ret;
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}
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rt_used
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static rt_uint64_t arm_arch_timer_get_value(void)
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{
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rt_uint64_t val = 0;
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if (arm_arch_timer_value_handle)
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{
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val = arm_arch_timer_value_handle(0);
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}
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return val;
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}
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static void arm_arch_timer_isr(int vector, void *param)
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{
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arm_arch_timer_set_value(timer_step);
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rt_tick_increase();
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}
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static int arm_arch_timer_post_init(void)
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{
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arm_arch_timer_local_enable();
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return 0;
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}
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INIT_SECONDARY_CPU_EXPORT(arm_arch_timer_post_init);
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static rt_err_t arm_arch_timer_probe(struct rt_platform_device *pdev)
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{
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int mode_idx, irq_idx;
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const char *irq_name[] =
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{
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"phys", /* Secure Phys IRQ */
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"virt", /* Non-secure Phys IRQ */
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"hyp-phys", /* Virt IRQ */
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"hyp-virt", /* Hyp IRQ */
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};
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#if defined(ARCH_SUPPORT_TEE)
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mode_idx = 0;
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irq_idx = 0;
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#elif defined(ARCH_SUPPORT_HYP)
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mode_idx = 2;
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irq_idx = 3;
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#else
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mode_idx = 5;
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irq_idx = 1;
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#endif
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arm_arch_timer_irq = rt_dm_dev_get_irq_by_name(&pdev->parent, irq_name[irq_idx]);
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if (arm_arch_timer_irq < 0)
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{
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arm_arch_timer_irq = rt_dm_dev_get_irq(&pdev->parent, irq_idx);
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}
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if (arm_arch_timer_irq < 0)
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{
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return -RT_EEMPTY;
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}
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arm_arch_timer_ctrl_handle = ctrl_handle[mode_idx];
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arm_arch_timer_value_handle = value_handle[mode_idx];
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rt_hw_interrupt_install(arm_arch_timer_irq, arm_arch_timer_isr, RT_NULL, "tick-arm-timer");
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timer_step = arm_arch_timer_get_frequency() / RT_TICK_PER_SECOND;
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arm_arch_timer_local_enable();
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return RT_EOK;
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}
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static const struct rt_ofw_node_id arm_arch_timer_ofw_ids[] =
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{
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{ .compatible = "arm,armv7-timer", },
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{ .compatible = "arm,armv8-timer", },
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{ /* sentinel */ }
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};
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static struct rt_platform_driver arm_arch_timer_driver =
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{
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.name = "arm-arch-timer",
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.ids = arm_arch_timer_ofw_ids,
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.probe = arm_arch_timer_probe,
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};
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static int arm_arch_timer_drv_register(void)
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{
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rt_platform_driver_register(&arm_arch_timer_driver);
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return 0;
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}
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INIT_SUBSYS_EXPORT(arm_arch_timer_drv_register);
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