86 lines
3.4 KiB
C
86 lines
3.4 KiB
C
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/*
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* Copyright (c) 2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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//! @addtogroup cortexa9
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//! @{
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/*!
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* @file arm_cp_registers.h
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* @brief Definitions for ARM coprocessor registers.
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*/
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#ifndef __ARM_CP_REGISTERS_H__
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#define __ARM_CP_REGISTERS_H__
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////////////////////////////////////////////////////////////////////////////////
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// Definitions
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////////////////////////////////////////////////////////////////////////////////
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//! @name ACTLR
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//@{
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#define BM_ACTLR_SMP (1 << 6)
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//@}
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//! @name DFSR
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//@{
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#define BM_DFSR_WNR (1 << 11) //!< Write not Read bit. 0=read, 1=write.
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#define BM_DFSR_FS4 (0x400) //!< Fault status bit 4..
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#define BP_DFSR_FS4 (10) //!< Bit position for FS[4].
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#define BM_DFSR_FS (0xf) //!< Fault status bits [3:0].
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//@}
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//! @name SCTLR
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//@{
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#define BM_SCTLR_TE (1 << 30) //!< Thumb exception enable.
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#define BM_SCTLR_AFE (1 << 29) //!< Access flag enable.
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#define BM_SCTLR_TRE (1 << 28) //!< TEX remap enable.
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#define BM_SCTLR_NMFI (1 << 27) //!< Non-maskable FIQ support.
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#define BM_SCTLR_EE (1 << 25) //!< Exception endianess.
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#define BM_SCTLR_VE (1 << 24) //!< Interrupt vectors enable.
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#define BM_SCTLR_FI (1 << 21) //!< Fast interrupt configurable enable.
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#define BM_SCTLR_RR (1 << 14) //!< Round Robin
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#define BM_SCTLR_V (1 << 13) //!< Vectors
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#define BM_SCTLR_I (1 << 12) //!< Instruction cache enable
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#define BM_SCTLR_Z (1 << 11) //!< Branch prediction enable
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#define BM_SCTLR_SW (1 << 10) //!< SWP and SWPB enable
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#define BM_SCTLR_CP15BEN (1 << 5) //!< CP15 barrier enable
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#define BM_SCTLR_C (1 << 2) //!< Data cache enable
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#define BM_SCTLR_A (1 << 1) //!< Alignment check enable
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#define BM_SCTLR_M (1 << 0) //!< MMU enable
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//@}
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//! @}
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#endif // __ARM_CP_REGISTERS_H__
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////////////////////////////////////////////////////////////////////////////////
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// EOF
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////////////////////////////////////////////////////////////////////////////////
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