76 lines
3.0 KiB
C
76 lines
3.0 KiB
C
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#ifndef __SWM320_SPI_H__
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#define __SWM320_SPI_H__
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typedef struct
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{
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uint8_t FrameFormat; //֡<><D6A1>ʽ<EFBFBD><CABD>SPI_FORMAT_SPI<50><49>SPI_FORMAT_TI_SSI
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uint8_t SampleEdge; //<2F><>SPI֡<49><D6A1>ʽ<EFBFBD>£<EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD><EFBFBD>ݲ<EFBFBD><DDB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>أ<EFBFBD>SPI_FIRST_EDGE<47><45>SPI_SECOND_EDGE
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uint8_t IdleLevel; //<2F><>SPI֡<49><D6A1>ʽ<EFBFBD>£<EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD><DDB4><EFBFBD>ʱ<EFBFBD><CAB1>ʱ<EFBFBD><CAB1><EFBFBD>ߵĵ<DFB5>ƽ<EFBFBD><C6BD>SPI_LOW_LEVEL<45><4C>SPI_HIGH_LEVEL
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uint8_t WordSize; //<2F>ֳ<EFBFBD><D6B3><EFBFBD>, <20><>Чֵ4-16
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uint8_t Master; //1 <20><><EFBFBD><EFBFBD>ģʽ 0 <20>ӻ<EFBFBD>ģʽ
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uint8_t clkDiv; //SPI_CLK = SYS_CLK / clkDiv<69><76><EFBFBD><EFBFBD>Чֵ<D0A7><D6B5>SPI_CLKDIV_4<5F><34>SPI_CLKDIV_8<5F><38>... ... <20><>SPI_CLKDIV_512
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uint8_t RXHFullIEn; //<2F><><EFBFBD><EFBFBD>FIFO<46><4F><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
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uint8_t TXEmptyIEn; //<2F><><EFBFBD><EFBFBD>FIFO <20><><EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
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uint8_t TXCompleteIEn; //<2F><><EFBFBD><EFBFBD>FIFO <20><><EFBFBD>ҷ<EFBFBD><D2B7><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
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} SPI_InitStructure;
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#define SPI_FORMAT_SPI 0 //Motorola SPI <20><>ʽ
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#define SPI_FORMAT_TI_SSI 1 //TI SSI <20><>ʽ
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#define SPI_FIRST_EDGE 0 //<2F><>һ<EFBFBD><D2BB>ʱ<EFBFBD><CAB1><EFBFBD>ؿ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
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#define SPI_SECOND_EDGE 1 //<2F>ڶ<EFBFBD><DAB6><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ؿ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
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#define SPI_LOW_LEVEL 0 //<2F><><EFBFBD><EFBFBD>ʱʱ<CAB1><CAB1><EFBFBD>߱<EFBFBD><DFB1>ֵ͵<D6B5>ƽ
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#define SPI_HIGH_LEVEL 1 //<2F><><EFBFBD><EFBFBD>ʱʱ<CAB1><CAB1><EFBFBD>߱<EFBFBD><DFB1>ָߵ<D6B8>ƽ
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#define SPI_CLKDIV_4 0
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#define SPI_CLKDIV_8 1
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#define SPI_CLKDIV_16 2
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#define SPI_CLKDIV_32 3
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#define SPI_CLKDIV_64 4
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#define SPI_CLKDIV_128 5
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#define SPI_CLKDIV_256 6
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#define SPI_CLKDIV_512 7
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void SPI_Init(SPI_TypeDef *SPIx, SPI_InitStructure *initStruct); //SPI<50><49>ʼ<EFBFBD><CABC>
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void SPI_Open(SPI_TypeDef *SPIx); //SPI<50><EFBFBD><F2BFAAA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>շ<EFBFBD>
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void SPI_Close(SPI_TypeDef *SPIx); //SPI<50>رգ<D8B1><D5A3><EFBFBD>ֹ<EFBFBD>շ<EFBFBD>
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uint32_t SPI_Read(SPI_TypeDef *SPIx);
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void SPI_Write(SPI_TypeDef *SPIx, uint32_t data);
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void SPI_WriteWithWait(SPI_TypeDef *SPIx, uint32_t data);
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uint32_t SPI_ReadWrite(SPI_TypeDef *SPIx, uint32_t data);
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uint32_t SPI_IsRXEmpty(SPI_TypeDef *SPIx); //<2F><><EFBFBD><EFBFBD>FIFO<46>Ƿ<EFBFBD><C7B7>գ<EFBFBD><D5A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD>SPI_Read()
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uint32_t SPI_IsTXFull(SPI_TypeDef *SPIx); //<2F><><EFBFBD><EFBFBD>FIFO<46>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD>SPI_Write()
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uint32_t SPI_IsTXEmpty(SPI_TypeDef *SPIx); //<2F><><EFBFBD><EFBFBD>FIFO<46>Ƿ<EFBFBD><C7B7><EFBFBD>
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void SPI_INTRXHalfFullEn(SPI_TypeDef *SPIx);
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void SPI_INTRXHalfFullDis(SPI_TypeDef *SPIx);
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uint32_t SPI_INTRXHalfFullStat(SPI_TypeDef *SPIx);
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void SPI_INTRXFullEn(SPI_TypeDef *SPIx);
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void SPI_INTRXFullDis(SPI_TypeDef *SPIx);
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uint32_t SPI_INTRXFullStat(SPI_TypeDef *SPIx);
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void SPI_INTRXOverflowEn(SPI_TypeDef *SPIx);
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void SPI_INTRXOverflowDis(SPI_TypeDef *SPIx);
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void SPI_INTRXOverflowClr(SPI_TypeDef *SPIx);
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uint32_t SPI_INTRXOverflowStat(SPI_TypeDef *SPIx);
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void SPI_INTTXHalfFullEn(SPI_TypeDef *SPIx);
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void SPI_INTTXHalfFullDis(SPI_TypeDef *SPIx);
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uint32_t SPI_INTTXHalfFullStat(SPI_TypeDef *SPIx);
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void SPI_INTTXEmptyEn(SPI_TypeDef *SPIx);
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void SPI_INTTXEmptyDis(SPI_TypeDef *SPIx);
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uint32_t SPI_INTTXEmptyStat(SPI_TypeDef *SPIx);
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void SPI_INTTXCompleteEn(SPI_TypeDef *SPIx);
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void SPI_INTTXCompleteDis(SPI_TypeDef *SPIx);
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void SPI_INTTXCompleteClr(SPI_TypeDef *SPIx);
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uint32_t SPI_INTTXCompleteStat(SPI_TypeDef *SPIx);
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#endif //__SWM320_SPI_H__
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