2021-09-02 09:55:07 +08:00
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/*
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2023-03-20 12:04:18 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2021-09-02 09:55:07 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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2023-04-05 12:18:51 +08:00
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* Date Author Notes
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* 2020-08-20 Abbcc first version
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* 2022-07-15 Aligagago add apm32F4 series MCU support
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* 2022-12-26 luobeihai add apm32F0 series MCU support
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* 2022-03-18 luobeihai fix warning about incompatible function pointer types
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* 2023-03-27 luobeihai add APM32E1/S1 series MCU support
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2021-09-02 09:55:07 +08:00
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*/
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#include <board.h>
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#include "drv_gpio.h"
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#ifdef RT_USING_PIN
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#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
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#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
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#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
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2021-09-05 21:40:55 +08:00
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#define PIN_APMPORT(pin) ((GPIO_T *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
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#define PIN_APMPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
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2021-09-02 09:55:07 +08:00
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#if defined(GPIOZ)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 12u
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2021-09-02 09:55:07 +08:00
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#elif defined(GPIOK)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 11u
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2021-09-02 09:55:07 +08:00
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#elif defined(GPIOJ)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 10u
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2021-09-02 09:55:07 +08:00
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#elif defined(GPIOI)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 9u
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2021-09-02 09:55:07 +08:00
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#elif defined(GPIOH)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 8u
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2021-09-02 09:55:07 +08:00
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#elif defined(GPIOG)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 7u
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2021-09-02 09:55:07 +08:00
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#elif defined(GPIOF)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 6u
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2021-09-02 09:55:07 +08:00
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#elif defined(GPIOE)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 5u
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2021-09-02 09:55:07 +08:00
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#elif defined(GPIOD)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 4u
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2021-09-02 09:55:07 +08:00
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#elif defined(GPIOC)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 3u
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2021-09-02 09:55:07 +08:00
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#elif defined(GPIOB)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 2u
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2021-09-02 09:55:07 +08:00
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#elif defined(GPIOA)
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 1u
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2021-09-02 09:55:07 +08:00
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#else
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2021-09-05 21:40:55 +08:00
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#define __APM32_PORT_MAX 0u
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#error Unsupported APM32 GPIO peripheral.
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2021-09-02 09:55:07 +08:00
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#endif
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2021-09-05 21:40:55 +08:00
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#define PIN_APMPORT_MAX __APM32_PORT_MAX
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2021-09-02 09:55:07 +08:00
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static const struct pin_irq_map pin_irq_map[] =
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{
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2023-01-05 14:15:02 +08:00
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#if defined(SOC_SERIES_APM32F0)
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{GPIO_PIN_0, EINT0_1_IRQn},
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{GPIO_PIN_1, EINT0_1_IRQn},
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{GPIO_PIN_2, EINT2_3_IRQn},
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{GPIO_PIN_3, EINT2_3_IRQn},
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{GPIO_PIN_4, EINT4_15_IRQn},
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{GPIO_PIN_5, EINT4_15_IRQn},
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{GPIO_PIN_6, EINT4_15_IRQn},
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{GPIO_PIN_7, EINT4_15_IRQn},
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{GPIO_PIN_8, EINT4_15_IRQn},
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{GPIO_PIN_9, EINT4_15_IRQn},
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{GPIO_PIN_10, EINT4_15_IRQn},
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{GPIO_PIN_11, EINT4_15_IRQn},
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{GPIO_PIN_12, EINT4_15_IRQn},
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{GPIO_PIN_13, EINT4_15_IRQn},
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{GPIO_PIN_14, EINT4_15_IRQn},
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2023-03-20 12:04:18 +08:00
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{GPIO_PIN_15, EINT4_15_IRQn},
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2023-04-05 12:18:51 +08:00
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#elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
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|| defined(SOC_SERIES_APM32F4)
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2021-09-02 09:55:07 +08:00
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{GPIO_PIN_0, EINT0_IRQn},
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{GPIO_PIN_1, EINT1_IRQn},
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{GPIO_PIN_2, EINT2_IRQn},
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{GPIO_PIN_3, EINT3_IRQn},
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{GPIO_PIN_4, EINT4_IRQn},
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{GPIO_PIN_5, EINT9_5_IRQn},
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{GPIO_PIN_6, EINT9_5_IRQn},
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{GPIO_PIN_7, EINT9_5_IRQn},
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{GPIO_PIN_8, EINT9_5_IRQn},
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{GPIO_PIN_9, EINT9_5_IRQn},
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{GPIO_PIN_10, EINT15_10_IRQn},
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{GPIO_PIN_11, EINT15_10_IRQn},
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{GPIO_PIN_12, EINT15_10_IRQn},
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{GPIO_PIN_13, EINT15_10_IRQn},
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{GPIO_PIN_14, EINT15_10_IRQn},
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{GPIO_PIN_15, EINT15_10_IRQn},
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2023-04-05 12:18:51 +08:00
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#endif /* SOC_SERIES_APM32F0 */
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2021-09-02 09:55:07 +08:00
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};
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static uint32_t pin_irq_enable_mask = 0;
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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2023-01-05 14:15:02 +08:00
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static rt_base_t apm32_pin_get(const char *name)
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2021-09-02 09:55:07 +08:00
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{
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rt_base_t pin = 0;
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int hw_port_num, hw_pin_num = 0;
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int i, name_len;
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name_len = rt_strlen(name);
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if ((name_len < 4) || (name_len >= 6))
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{
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return -RT_EINVAL;
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}
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if ((name[0] != 'P') || (name[2] != '.'))
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{
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return -RT_EINVAL;
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}
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if ((name[1] >= 'A') && (name[1] <= 'Z'))
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{
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hw_port_num = (int)(name[1] - 'A');
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}
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else
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{
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return -RT_EINVAL;
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}
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for (i = 3; i < name_len; i++)
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{
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hw_pin_num *= 10;
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hw_pin_num += name[i] - '0';
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}
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pin = PIN_NUM(hw_port_num, hw_pin_num);
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return pin;
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}
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2023-03-20 12:04:18 +08:00
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static void apm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
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2021-09-02 09:55:07 +08:00
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{
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GPIO_T *gpio_port;
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uint16_t gpio_pin;
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2021-09-05 21:40:55 +08:00
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if (PIN_PORT(pin) < PIN_APMPORT_MAX)
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2021-09-02 09:55:07 +08:00
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{
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2021-09-05 21:40:55 +08:00
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gpio_port = PIN_APMPORT(pin);
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gpio_pin = PIN_APMPIN(pin);
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2023-01-05 14:15:02 +08:00
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#if defined(SOC_SERIES_APM32F0)
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GPIO_WriteBitValue(gpio_port, gpio_pin, (GPIO_BSRET_T)value);
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2023-04-05 12:18:51 +08:00
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#elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
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|| defined(SOC_SERIES_APM32F4)
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2021-09-02 09:55:07 +08:00
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GPIO_WriteBitValue(gpio_port, gpio_pin, (uint8_t)value);
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2023-01-05 14:15:02 +08:00
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#endif
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2021-09-02 09:55:07 +08:00
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}
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}
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2024-03-24 02:50:31 +08:00
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static rt_ssize_t apm32_pin_read(rt_device_t dev, rt_base_t pin)
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2021-09-02 09:55:07 +08:00
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{
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GPIO_T *gpio_port;
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uint16_t gpio_pin;
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int value = PIN_LOW;
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2021-09-05 21:40:55 +08:00
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if (PIN_PORT(pin) < PIN_APMPORT_MAX)
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2021-09-02 09:55:07 +08:00
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{
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2021-09-05 21:40:55 +08:00
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gpio_port = PIN_APMPORT(pin);
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gpio_pin = PIN_APMPIN(pin);
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2021-09-02 09:55:07 +08:00
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value = GPIO_ReadInputBit(gpio_port, gpio_pin);
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}
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return value;
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}
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2023-03-20 12:04:18 +08:00
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static void apm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
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2021-09-02 09:55:07 +08:00
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{
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GPIO_Config_T gpioConfig;
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2021-09-05 21:40:55 +08:00
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if (PIN_PORT(pin) >= PIN_APMPORT_MAX)
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2021-09-02 09:55:07 +08:00
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{
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return;
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}
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/* Configure gpioConfigure */
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2023-04-05 12:18:51 +08:00
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#if defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1)
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2021-09-05 21:40:55 +08:00
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gpioConfig.pin = PIN_APMPIN(pin);
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2021-09-02 09:55:07 +08:00
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gpioConfig.mode = GPIO_MODE_OUT_PP;
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gpioConfig.speed = GPIO_SPEED_50MHz;
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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gpioConfig.mode = GPIO_MODE_OUT_PP;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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gpioConfig.mode = GPIO_MODE_IN_PU;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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gpioConfig.mode = GPIO_MODE_IN_PU;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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gpioConfig.mode = GPIO_MODE_IN_PD;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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gpioConfig.mode = GPIO_MODE_OUT_OD;
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}
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2023-01-05 14:15:02 +08:00
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#elif defined(SOC_SERIES_APM32F4)
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2022-07-22 15:05:14 +08:00
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gpioConfig.pin = PIN_APMPIN(pin);
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gpioConfig.mode = GPIO_MODE_OUT;
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gpioConfig.otype = GPIO_OTYPE_PP;
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gpioConfig.speed = GPIO_SPEED_50MHz;
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2021-09-02 09:55:07 +08:00
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2022-07-22 15:05:14 +08:00
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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gpioConfig.mode = GPIO_MODE_OUT;
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gpioConfig.otype = GPIO_OTYPE_PP;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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gpioConfig.mode = GPIO_MODE_IN;
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gpioConfig.pupd = GPIO_PUPD_NOPULL;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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gpioConfig.mode = GPIO_MODE_IN;
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gpioConfig.pupd = GPIO_PUPD_UP;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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gpioConfig.mode = GPIO_MODE_IN;
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gpioConfig.pupd = GPIO_PUPD_DOWN;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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gpioConfig.mode = GPIO_MODE_OUT;
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gpioConfig.otype = GPIO_OTYPE_OD;
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}
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2023-01-05 14:15:02 +08:00
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#elif defined(SOC_SERIES_APM32F0)
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gpioConfig.pin = PIN_APMPIN(pin);
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gpioConfig.mode = GPIO_MODE_OUT;
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gpioConfig.outtype = GPIO_OUT_TYPE_PP;
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gpioConfig.pupd = GPIO_PUPD_NO;
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gpioConfig.speed = GPIO_SPEED_50MHz;
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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gpioConfig.mode = GPIO_MODE_OUT;
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gpioConfig.outtype = GPIO_OUT_TYPE_PP;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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gpioConfig.mode = GPIO_MODE_IN;
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gpioConfig.pupd = GPIO_PUPD_NO;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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gpioConfig.mode = GPIO_MODE_IN;
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gpioConfig.pupd = GPIO_PUPD_PU;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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gpioConfig.mode = GPIO_MODE_IN;
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|
gpioConfig.pupd = GPIO_PUPD_PD;
|
|
|
|
}
|
|
|
|
else if (mode == PIN_MODE_OUTPUT_OD)
|
|
|
|
{
|
|
|
|
/* output setting: od. */
|
|
|
|
gpioConfig.mode = GPIO_MODE_OUT;
|
|
|
|
gpioConfig.outtype = GPIO_OUT_TYPE_OD;
|
|
|
|
}
|
2022-07-22 15:05:14 +08:00
|
|
|
#endif
|
2021-09-05 21:40:55 +08:00
|
|
|
GPIO_Config(PIN_APMPORT(pin), &gpioConfig);
|
2021-09-02 09:55:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
for (i = 0; i < 32; i++)
|
|
|
|
{
|
|
|
|
if ((0x01 << i) == bit)
|
|
|
|
{
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
|
|
|
|
{
|
|
|
|
rt_int32_t mapindex = bit2bitno(pinbit);
|
|
|
|
if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
|
|
|
|
{
|
|
|
|
return RT_NULL;
|
|
|
|
}
|
|
|
|
return &pin_irq_map[mapindex];
|
|
|
|
};
|
|
|
|
|
2023-03-20 12:04:18 +08:00
|
|
|
static rt_err_t apm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
|
|
|
|
rt_uint8_t mode, void (*hdr)(void *args), void *args)
|
2021-09-02 09:55:07 +08:00
|
|
|
{
|
|
|
|
rt_base_t level;
|
|
|
|
rt_int32_t irqindex = -1;
|
|
|
|
|
2021-09-05 21:40:55 +08:00
|
|
|
if (PIN_PORT(pin) >= PIN_APMPORT_MAX)
|
2021-09-02 09:55:07 +08:00
|
|
|
{
|
|
|
|
return -RT_ENOSYS;
|
|
|
|
}
|
|
|
|
|
2021-09-05 21:40:55 +08:00
|
|
|
irqindex = bit2bitno(PIN_APMPIN(pin));
|
2021-09-02 09:55:07 +08:00
|
|
|
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
|
|
|
|
{
|
2023-03-23 13:54:42 +08:00
|
|
|
return -RT_ENOSYS;
|
2021-09-02 09:55:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
level = rt_hw_interrupt_disable();
|
|
|
|
if (pin_irq_hdr_tab[irqindex].pin == pin &&
|
2021-09-05 21:40:55 +08:00
|
|
|
pin_irq_hdr_tab[irqindex].hdr == hdr &&
|
|
|
|
pin_irq_hdr_tab[irqindex].mode == mode &&
|
|
|
|
pin_irq_hdr_tab[irqindex].args == args)
|
2021-09-02 09:55:07 +08:00
|
|
|
{
|
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
if (pin_irq_hdr_tab[irqindex].pin != -1)
|
|
|
|
{
|
|
|
|
rt_hw_interrupt_enable(level);
|
2023-03-22 03:41:55 +08:00
|
|
|
return -RT_EBUSY;
|
2021-09-02 09:55:07 +08:00
|
|
|
}
|
|
|
|
pin_irq_hdr_tab[irqindex].pin = pin;
|
|
|
|
pin_irq_hdr_tab[irqindex].hdr = hdr;
|
|
|
|
pin_irq_hdr_tab[irqindex].mode = mode;
|
|
|
|
pin_irq_hdr_tab[irqindex].args = args;
|
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
2023-03-20 12:04:18 +08:00
|
|
|
static rt_err_t apm32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
|
2021-09-02 09:55:07 +08:00
|
|
|
{
|
|
|
|
rt_base_t level;
|
|
|
|
rt_int32_t irqindex = -1;
|
|
|
|
|
2021-09-05 21:40:55 +08:00
|
|
|
if (PIN_PORT(pin) >= PIN_APMPORT_MAX)
|
2021-09-02 09:55:07 +08:00
|
|
|
{
|
|
|
|
return -RT_ENOSYS;
|
|
|
|
}
|
|
|
|
|
2021-09-05 21:40:55 +08:00
|
|
|
irqindex = bit2bitno(PIN_APMPIN(pin));
|
2021-09-02 09:55:07 +08:00
|
|
|
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
|
|
|
|
{
|
2023-03-23 13:54:42 +08:00
|
|
|
return -RT_ENOSYS;
|
2021-09-02 09:55:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
level = rt_hw_interrupt_disable();
|
|
|
|
if (pin_irq_hdr_tab[irqindex].pin == -1)
|
|
|
|
{
|
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
pin_irq_hdr_tab[irqindex].pin = -1;
|
|
|
|
pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
|
|
|
|
pin_irq_hdr_tab[irqindex].mode = 0;
|
|
|
|
pin_irq_hdr_tab[irqindex].args = RT_NULL;
|
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
2023-01-05 14:15:02 +08:00
|
|
|
static rt_err_t apm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
|
2023-03-20 12:04:18 +08:00
|
|
|
rt_uint8_t enabled)
|
2021-09-02 09:55:07 +08:00
|
|
|
{
|
|
|
|
const struct pin_irq_map *irqmap;
|
|
|
|
rt_base_t level;
|
|
|
|
rt_int32_t irqindex = -1;
|
|
|
|
GPIO_Config_T gpioConfig;
|
2023-01-05 14:15:02 +08:00
|
|
|
EINT_Config_T eintConfig;
|
2021-09-02 09:55:07 +08:00
|
|
|
|
2021-09-05 21:40:55 +08:00
|
|
|
if (PIN_PORT(pin) >= PIN_APMPORT_MAX)
|
2021-09-02 09:55:07 +08:00
|
|
|
{
|
|
|
|
return -RT_ENOSYS;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (enabled == PIN_IRQ_ENABLE)
|
|
|
|
{
|
2021-09-05 21:40:55 +08:00
|
|
|
irqindex = bit2bitno(PIN_APMPIN(pin));
|
2021-09-02 09:55:07 +08:00
|
|
|
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
|
|
|
|
{
|
2023-03-23 13:54:42 +08:00
|
|
|
return -RT_ENOSYS;
|
2021-09-02 09:55:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
level = rt_hw_interrupt_disable();
|
|
|
|
|
|
|
|
if (pin_irq_hdr_tab[irqindex].pin == -1)
|
|
|
|
{
|
|
|
|
rt_hw_interrupt_enable(level);
|
2023-03-23 13:54:42 +08:00
|
|
|
return -RT_ENOSYS;
|
2021-09-02 09:55:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
irqmap = &pin_irq_map[irqindex];
|
|
|
|
|
|
|
|
/* Configure gpioConfigure */
|
2021-09-05 21:40:55 +08:00
|
|
|
gpioConfig.pin = PIN_APMPIN(pin);
|
2021-09-02 09:55:07 +08:00
|
|
|
gpioConfig.speed = GPIO_SPEED_50MHz;
|
|
|
|
switch (pin_irq_hdr_tab[irqindex].mode)
|
|
|
|
{
|
2023-01-05 14:15:02 +08:00
|
|
|
#if defined(SOC_SERIES_APM32F0)
|
|
|
|
case PIN_IRQ_MODE_RISING:
|
|
|
|
gpioConfig.mode = GPIO_MODE_IN;
|
|
|
|
gpioConfig.pupd = GPIO_PUPD_PD;
|
|
|
|
eintConfig.trigger = EINT_TRIGGER_RISING;
|
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_FALLING:
|
|
|
|
gpioConfig.mode = GPIO_MODE_IN;
|
|
|
|
gpioConfig.pupd = GPIO_PUPD_PU;
|
|
|
|
eintConfig.trigger = EINT_TRIGGER_FALLING;
|
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_RISING_FALLING:
|
|
|
|
gpioConfig.mode = GPIO_MODE_IN;
|
|
|
|
gpioConfig.pupd = GPIO_PUPD_NO;
|
|
|
|
eintConfig.trigger = EINT_TRIGGER_ALL;
|
|
|
|
break;
|
2023-04-05 12:18:51 +08:00
|
|
|
#elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1)
|
2022-07-25 10:21:18 +08:00
|
|
|
case PIN_IRQ_MODE_RISING:
|
|
|
|
gpioConfig.mode = GPIO_MODE_IN_PD;
|
2023-01-05 14:15:02 +08:00
|
|
|
eintConfig.trigger = EINT_TRIGGER_RISING;
|
2022-07-25 10:21:18 +08:00
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_FALLING:
|
|
|
|
gpioConfig.mode = GPIO_MODE_IN_PU;
|
2023-01-05 14:15:02 +08:00
|
|
|
eintConfig.trigger = EINT_TRIGGER_FALLING;
|
2022-07-25 10:21:18 +08:00
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_RISING_FALLING:
|
|
|
|
gpioConfig.mode = GPIO_MODE_IN_FLOATING;
|
2023-01-05 14:15:02 +08:00
|
|
|
eintConfig.trigger = EINT_TRIGGER_RISING_FALLING;
|
2022-07-25 10:21:18 +08:00
|
|
|
break;
|
2023-01-05 14:15:02 +08:00
|
|
|
#elif defined(SOC_SERIES_APM32F4)
|
2022-07-25 10:21:18 +08:00
|
|
|
case PIN_IRQ_MODE_RISING:
|
|
|
|
gpioConfig.mode = GPIO_MODE_IN;
|
|
|
|
gpioConfig.pupd = GPIO_PUPD_DOWN;
|
2023-01-05 14:15:02 +08:00
|
|
|
eintConfig.trigger = EINT_TRIGGER_RISING;
|
2022-07-25 10:21:18 +08:00
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_FALLING:
|
|
|
|
gpioConfig.mode = GPIO_MODE_IN;
|
|
|
|
gpioConfig.pupd = GPIO_PUPD_UP;
|
2023-01-05 14:15:02 +08:00
|
|
|
eintConfig.trigger = EINT_TRIGGER_FALLING;
|
2022-07-25 10:21:18 +08:00
|
|
|
break;
|
|
|
|
case PIN_IRQ_MODE_RISING_FALLING:
|
|
|
|
gpioConfig.mode = GPIO_MODE_IN;
|
|
|
|
gpioConfig.pupd = GPIO_PUPD_NOPULL;
|
2023-01-05 14:15:02 +08:00
|
|
|
eintConfig.trigger = EINT_TRIGGER_RISING_FALLING;
|
2022-07-25 10:21:18 +08:00
|
|
|
break;
|
|
|
|
#endif
|
2021-09-02 09:55:07 +08:00
|
|
|
}
|
2021-09-05 21:40:55 +08:00
|
|
|
GPIO_Config(PIN_APMPORT(pin), &gpioConfig);
|
2023-03-20 12:04:18 +08:00
|
|
|
|
2023-01-05 14:15:02 +08:00
|
|
|
#if defined(SOC_SERIES_APM32F0)
|
|
|
|
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SYSCFG);
|
|
|
|
SYSCFG_EINTLine((SYSCFG_PORT_T)(((pin) >> 4) & 0xFu), (SYSCFG_PIN_T)irqindex);
|
2023-04-05 12:18:51 +08:00
|
|
|
#elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1)
|
2023-01-05 14:15:02 +08:00
|
|
|
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_AFIO);
|
|
|
|
GPIO_ConfigEINTLine((GPIO_PORT_SOURCE_T)(((pin) >> 4) & 0xFu), (GPIO_PIN_SOURCE_T)irqindex);
|
|
|
|
#elif defined(SOC_SERIES_APM32F4)
|
|
|
|
RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SYSCFG);
|
|
|
|
SYSCFG_ConfigEINTLine((SYSCFG_PORT_T)(((pin) >> 4) & 0xFu), (SYSCFG_PIN_T)irqindex);
|
|
|
|
#endif
|
|
|
|
eintConfig.line = (EINT_LINE_T)(1u << PIN_NO(pin));
|
|
|
|
eintConfig.mode = EINT_MODE_INTERRUPT;
|
|
|
|
eintConfig.lineCmd = ENABLE;
|
|
|
|
EINT_Config(&eintConfig);
|
2023-03-20 12:04:18 +08:00
|
|
|
|
2023-01-05 14:15:02 +08:00
|
|
|
#if defined(SOC_SERIES_APM32F0)
|
|
|
|
NVIC_EnableIRQRequest(irqmap->irqno, 5);
|
2023-04-05 12:18:51 +08:00
|
|
|
#elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
|
|
|
|
|| defined(SOC_SERIES_APM32F4)
|
2021-09-02 09:55:07 +08:00
|
|
|
NVIC_EnableIRQRequest(irqmap->irqno, 5, 0);
|
2023-01-05 14:15:02 +08:00
|
|
|
#endif
|
2021-09-02 09:55:07 +08:00
|
|
|
pin_irq_enable_mask |= irqmap->pinbit;
|
|
|
|
|
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
}
|
|
|
|
else if (enabled == PIN_IRQ_DISABLE)
|
|
|
|
{
|
2021-09-05 21:40:55 +08:00
|
|
|
irqmap = get_pin_irq_map(PIN_APMPIN(pin));
|
2021-09-02 09:55:07 +08:00
|
|
|
if (irqmap == RT_NULL)
|
|
|
|
{
|
2023-03-23 13:54:42 +08:00
|
|
|
return -RT_ENOSYS;
|
2021-09-02 09:55:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
level = rt_hw_interrupt_disable();
|
2021-09-05 21:40:55 +08:00
|
|
|
|
2021-09-02 09:55:07 +08:00
|
|
|
pin_irq_enable_mask &= ~irqmap->pinbit;
|
2023-03-20 12:04:18 +08:00
|
|
|
|
2023-01-05 14:15:02 +08:00
|
|
|
#if defined(SOC_SERIES_APM32F0)
|
|
|
|
if ((irqmap->pinbit >= GPIO_PIN_0) && (irqmap->pinbit <= GPIO_PIN_1))
|
|
|
|
{
|
|
|
|
if (!(pin_irq_enable_mask & (GPIO_PIN_0 | GPIO_PIN_1)))
|
|
|
|
{
|
|
|
|
NVIC_DisableIRQRequest(irqmap->irqno);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if ((irqmap->pinbit >= GPIO_PIN_2) && (irqmap->pinbit <= GPIO_PIN_3))
|
|
|
|
{
|
|
|
|
if (!(pin_irq_enable_mask & (GPIO_PIN_2 | GPIO_PIN_3)))
|
|
|
|
{
|
|
|
|
NVIC_DisableIRQRequest(irqmap->irqno);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if ((irqmap->pinbit >= GPIO_PIN_4) && (irqmap->pinbit <= GPIO_PIN_15))
|
|
|
|
{
|
|
|
|
if (!(pin_irq_enable_mask & (GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 |
|
|
|
|
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
|
|
|
|
{
|
|
|
|
NVIC_DisableIRQRequest(irqmap->irqno);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
NVIC_DisableIRQRequest(irqmap->irqno);
|
|
|
|
}
|
2023-04-05 12:18:51 +08:00
|
|
|
#elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
|
|
|
|
|| defined(SOC_SERIES_APM32F4)
|
2021-09-02 09:55:07 +08:00
|
|
|
if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
|
|
|
|
{
|
|
|
|
if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
|
|
|
|
{
|
|
|
|
NVIC_DisableIRQRequest(irqmap->irqno);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
|
|
|
|
{
|
|
|
|
if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
|
|
|
|
{
|
|
|
|
NVIC_DisableIRQRequest(irqmap->irqno);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
NVIC_DisableIRQRequest(irqmap->irqno);
|
|
|
|
}
|
2023-04-05 12:18:51 +08:00
|
|
|
#endif /* SOC_SERIES_APM32F0 */
|
2021-09-02 09:55:07 +08:00
|
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
return -RT_ENOSYS;
|
|
|
|
}
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
2023-01-05 14:15:02 +08:00
|
|
|
|
|
|
|
const static struct rt_pin_ops apm32_pin_ops =
|
2021-09-02 09:55:07 +08:00
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{
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2023-01-05 14:15:02 +08:00
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apm32_pin_mode,
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apm32_pin_write,
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apm32_pin_read,
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apm32_pin_attach_irq,
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apm32_pin_dettach_irq,
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apm32_pin_irq_enable,
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apm32_pin_get,
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2021-09-02 09:55:07 +08:00
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};
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rt_inline void pin_irq_hdr(int irqno)
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{
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if (pin_irq_hdr_tab[irqno].hdr)
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{
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pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
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}
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}
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2023-01-05 14:15:02 +08:00
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void GPIO_EXTI_IRQHandler(uint8_t exti_line)
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2021-09-02 09:55:07 +08:00
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{
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2023-01-05 14:15:02 +08:00
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#if defined(SOC_SERIES_APM32F0)
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if (EINT_ReadIntFlag(1U << exti_line) != RESET)
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2023-04-05 12:18:51 +08:00
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#elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
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|| defined(SOC_SERIES_APM32F4)
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2023-01-05 14:15:02 +08:00
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if (EINT_ReadIntFlag((EINT_LINE_T)(1U << exti_line)) != RESET)
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#endif
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{
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EINT_ClearIntFlag(1U << exti_line);
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pin_irq_hdr(exti_line);
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}
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2021-09-02 09:55:07 +08:00
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}
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2023-01-05 14:15:02 +08:00
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#if defined(SOC_SERIES_APM32F0)
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void EINT0_1_IRQHandler(void)
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{
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rt_interrupt_enter();
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GPIO_EXTI_IRQHandler(0);
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GPIO_EXTI_IRQHandler(1);
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rt_interrupt_leave();
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}
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2021-09-02 09:55:07 +08:00
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2023-01-05 14:15:02 +08:00
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void EINT2_3_IRQHandler(void)
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{
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rt_interrupt_enter();
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GPIO_EXTI_IRQHandler(2);
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GPIO_EXTI_IRQHandler(3);
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rt_interrupt_leave();
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}
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void EINT4_15_IRQHandler(void)
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{
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rt_interrupt_enter();
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GPIO_EXTI_IRQHandler(4);
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GPIO_EXTI_IRQHandler(5);
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GPIO_EXTI_IRQHandler(6);
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GPIO_EXTI_IRQHandler(7);
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GPIO_EXTI_IRQHandler(8);
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GPIO_EXTI_IRQHandler(9);
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GPIO_EXTI_IRQHandler(10);
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GPIO_EXTI_IRQHandler(11);
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GPIO_EXTI_IRQHandler(12);
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GPIO_EXTI_IRQHandler(13);
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GPIO_EXTI_IRQHandler(14);
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GPIO_EXTI_IRQHandler(15);
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rt_interrupt_leave();
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}
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2023-04-05 12:18:51 +08:00
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#elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
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|| defined(SOC_SERIES_APM32F4)
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2021-09-02 09:55:07 +08:00
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void EINT0_IRQHandler(void)
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{
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rt_interrupt_enter();
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2023-01-05 14:15:02 +08:00
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GPIO_EXTI_IRQHandler(0);
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2021-09-02 09:55:07 +08:00
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rt_interrupt_leave();
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}
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void EINT1_IRQHandler(void)
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{
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rt_interrupt_enter();
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2023-01-05 14:15:02 +08:00
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GPIO_EXTI_IRQHandler(1);
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2021-09-02 09:55:07 +08:00
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rt_interrupt_leave();
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}
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void EINT2_IRQHandler(void)
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{
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rt_interrupt_enter();
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2023-01-05 14:15:02 +08:00
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GPIO_EXTI_IRQHandler(2);
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2021-09-02 09:55:07 +08:00
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rt_interrupt_leave();
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}
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void EINT3_IRQHandler(void)
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{
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rt_interrupt_enter();
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2023-01-05 14:15:02 +08:00
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GPIO_EXTI_IRQHandler(3);
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2021-09-02 09:55:07 +08:00
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rt_interrupt_leave();
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}
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void EINT4_IRQHandler(void)
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{
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rt_interrupt_enter();
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2023-01-05 14:15:02 +08:00
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GPIO_EXTI_IRQHandler(4);
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2021-09-02 09:55:07 +08:00
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rt_interrupt_leave();
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}
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void EINT9_5_IRQHandler(void)
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{
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rt_interrupt_enter();
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2023-01-05 14:15:02 +08:00
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GPIO_EXTI_IRQHandler(5);
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GPIO_EXTI_IRQHandler(6);
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GPIO_EXTI_IRQHandler(7);
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GPIO_EXTI_IRQHandler(8);
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GPIO_EXTI_IRQHandler(9);
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2021-09-02 09:55:07 +08:00
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rt_interrupt_leave();
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}
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void EINT15_10_IRQHandler(void)
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{
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rt_interrupt_enter();
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2023-01-05 14:15:02 +08:00
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GPIO_EXTI_IRQHandler(10);
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GPIO_EXTI_IRQHandler(11);
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GPIO_EXTI_IRQHandler(12);
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GPIO_EXTI_IRQHandler(13);
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GPIO_EXTI_IRQHandler(14);
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GPIO_EXTI_IRQHandler(15);
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2021-09-02 09:55:07 +08:00
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rt_interrupt_leave();
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}
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2023-01-05 14:15:02 +08:00
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#endif
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2021-09-02 09:55:07 +08:00
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int rt_hw_pin_init(void)
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{
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2023-04-05 12:18:51 +08:00
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#if defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1)
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2022-07-25 10:21:18 +08:00
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#ifdef GPIOA
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA);
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#endif
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#ifdef GPIOB
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOB);
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#endif
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#ifdef GPIOC
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOC);
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#endif
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#ifdef GPIOD
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOD);
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#endif
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#ifdef GPIOE
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOE);
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#endif
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#ifdef GPIOF
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOF);
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#endif
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#ifdef GPIOG
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOG);
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#endif
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RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_AFIO);
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2023-01-05 14:15:02 +08:00
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#elif defined(SOC_SERIES_APM32F4)
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2022-07-25 10:21:18 +08:00
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#ifdef GPIOA
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RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOA);
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#endif
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#ifdef GPIOB
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RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOB);
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#endif
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#ifdef GPIOC
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RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOC);
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#endif
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#ifdef GPIOD
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RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOD);
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#endif
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#ifdef GPIOE
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RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOE);
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#endif
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#ifdef GPIOF
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RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOF);
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#endif
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#ifdef GPIOG
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RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOG);
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#endif
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#ifdef GPIOH
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RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOH);
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#endif
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#ifdef GPIOI
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RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOI);
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#endif
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#ifdef GPIOJ
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RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOJ);
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#endif
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#ifdef GPIOK
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RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOK);
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#endif
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2023-01-05 14:15:02 +08:00
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#elif defined(SOC_SERIES_APM32F0)
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#ifdef GPIOA
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RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOA);
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#endif
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#ifdef GPIOB
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RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOB);
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2021-09-02 09:55:07 +08:00
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#endif
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2023-01-05 14:15:02 +08:00
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#ifdef GPIOC
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RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOC);
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#endif
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#ifdef GPIOD
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RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOD);
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#endif
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#ifdef GPIOE
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RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOE);
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#endif
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#ifdef GPIOF
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RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOF);
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#endif
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#endif /* SOC_SERIES_APM32F0 */
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2021-09-02 09:55:07 +08:00
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2023-01-05 14:15:02 +08:00
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return rt_device_pin_register("pin", &apm32_pin_ops, RT_NULL);
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2021-09-02 09:55:07 +08:00
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}
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#endif /* RT_USING_PIN */
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