2021-08-23 10:13:53 +08:00
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/*
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2022-03-26 15:40:33 +08:00
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* Copyright (c) 2006-2022, RT-Thread Development Team
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2021-08-23 10:13:53 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-26 AisinoChip first version
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2022-03-26 15:40:33 +08:00
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* 2021-10-15 AisinoChip add special pin setting
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2021-08-23 10:13:53 +08:00
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <rtconfig.h>
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#include "board.h"
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#ifdef RT_USING_PIN
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#include <rtdevice.h>
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#define __ACM32_PIN(index, gpio, gpio_index) \
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{ \
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index, GPIO##gpio, GPIO_PIN_##gpio_index \
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}
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#define __ACM32_PIN_RESERVE \
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{ \
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-1, 0, 0 \
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}
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/* ACM32 GPIO driver */
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struct pin_index
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{
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int index;
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enum_GPIOx_t gpio;
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uint32_t pin;
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};
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struct pin_irq_map
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{
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rt_uint16_t line;
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EXTI_HandleTypeDef handle;
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};
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static const struct pin_index pins[] =
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{
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#if defined(BSP_USING_GPIO1)
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__ACM32_PIN(0, A, 0),
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__ACM32_PIN(1, A, 1),
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__ACM32_PIN(2, A, 2),
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__ACM32_PIN(3, A, 3),
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__ACM32_PIN(4, A, 4),
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__ACM32_PIN(5, A, 5),
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__ACM32_PIN(6, A, 6),
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__ACM32_PIN(7, A, 7),
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__ACM32_PIN(8, A, 8),
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__ACM32_PIN(9, A, 9),
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__ACM32_PIN(10, A, 10),
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__ACM32_PIN(11, A, 11),
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__ACM32_PIN(12, A, 12),
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__ACM32_PIN(13, A, 13),
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__ACM32_PIN(14, A, 14),
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__ACM32_PIN(15, A, 15),
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__ACM32_PIN(16, B, 0),
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__ACM32_PIN(17, B, 1),
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__ACM32_PIN(18, B, 2),
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__ACM32_PIN(19, B, 3),
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__ACM32_PIN(20, B, 4),
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__ACM32_PIN(21, B, 5),
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__ACM32_PIN(22, B, 6),
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__ACM32_PIN(23, B, 7),
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__ACM32_PIN(24, B, 8),
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__ACM32_PIN(25, B, 9),
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__ACM32_PIN(26, B, 10),
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__ACM32_PIN(27, B, 11),
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__ACM32_PIN(28, B, 12),
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__ACM32_PIN(29, B, 13),
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__ACM32_PIN(30, B, 14),
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__ACM32_PIN(31, B, 15),
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#if defined(BSP_USING_GPIO2)
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__ACM32_PIN(32, C, 0),
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__ACM32_PIN(33, C, 1),
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__ACM32_PIN(34, C, 2),
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__ACM32_PIN(35, C, 3),
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__ACM32_PIN(36, C, 4),
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__ACM32_PIN(37, C, 5),
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__ACM32_PIN(38, C, 6),
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__ACM32_PIN(39, C, 7),
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__ACM32_PIN(40, C, 8),
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__ACM32_PIN(41, C, 9),
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__ACM32_PIN(42, C, 10),
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__ACM32_PIN(43, C, 11),
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__ACM32_PIN(44, C, 12),
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__ACM32_PIN(45, C, 13),
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__ACM32_PIN(46, C, 14),
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__ACM32_PIN(47, C, 15),
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__ACM32_PIN(48, D, 0),
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__ACM32_PIN(49, D, 1),
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__ACM32_PIN(50, D, 2),
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__ACM32_PIN(51, D, 3),
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__ACM32_PIN(52, D, 4),
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__ACM32_PIN(53, D, 5),
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__ACM32_PIN(54, D, 6),
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__ACM32_PIN(55, D, 7),
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__ACM32_PIN(56, D, 8),
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__ACM32_PIN(57, D, 9),
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__ACM32_PIN(58, D, 10),
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__ACM32_PIN(59, D, 11),
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__ACM32_PIN(60, D, 12),
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__ACM32_PIN(61, D, 13),
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__ACM32_PIN(62, D, 14),
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__ACM32_PIN(63, D, 15),
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#endif /* defined(BSP_USING_GPIO2) */
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#endif /* defined(BSP_USING_GPIO1) */
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};
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static struct pin_irq_map pin_irq_map[] =
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{
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{EXTI_LINE_0, {0}},
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{EXTI_LINE_1, {0}},
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{EXTI_LINE_2, {0}},
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{EXTI_LINE_3, {0}},
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{EXTI_LINE_4, {0}},
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{EXTI_LINE_5, {0}},
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{EXTI_LINE_6, {0}},
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{EXTI_LINE_7, {0}},
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{EXTI_LINE_8, {0}},
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{EXTI_LINE_9, {0}},
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{EXTI_LINE_10, {0}},
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{EXTI_LINE_11, {0}},
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{EXTI_LINE_12, {0}},
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{EXTI_LINE_13, {0}},
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{EXTI_LINE_14, {0}},
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{EXTI_LINE_15, {0}},
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};
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static uint32_t pin_irq_enable_mask = 0;
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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static const struct pin_index *get_pin(uint8_t pin)
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{
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const struct pin_index *index;
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if (pin < ITEM_NUM(pins))
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{
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index = &pins[pin];
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if (index->index == -1)
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index = RT_NULL;
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}
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else
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{
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index = RT_NULL;
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}
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return index;
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};
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2023-04-07 11:42:05 +08:00
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static void acm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
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2021-08-23 10:13:53 +08:00
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{
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const struct pin_index *index;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value);
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}
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2024-03-24 02:50:31 +08:00
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static rt_ssize_t acm32_pin_read(rt_device_t dev, rt_base_t pin)
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2021-08-23 10:13:53 +08:00
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{
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int value;
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const struct pin_index *index;
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value = PIN_LOW;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return value;
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}
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value = HAL_GPIO_ReadPin(index->gpio, index->pin);
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return value;
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}
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2023-04-07 11:42:05 +08:00
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static void acm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
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2021-08-23 10:13:53 +08:00
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{
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const struct pin_index *index;
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GPIO_InitTypeDef GPIO_InitStruct;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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/* Configure GPIO_InitStructure */
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GPIO_InitStruct.Pin = index->pin;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_PULLUP;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_PULLDOWN;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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}
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/* special PIN process */
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2022-03-26 15:40:33 +08:00
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if(index->gpio == GPIOC && index->pin == GPIO_PIN_13)
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{
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__HAL_RTC_PC13_DIGIT();
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__HAL_RTC_PC13_SEL(0); /* GPIO function */
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__HAL_RTC_PC13_PULL_DOWN_DISABLE();
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__HAL_RTC_PC13_PULL_UP_DISABLE();
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if(GPIO_InitStruct.Pull == GPIO_PULLUP)
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{
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__HAL_RTC_PC13_PULL_UP_ENABLE();
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}
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else if(GPIO_InitStruct.Pull == GPIO_PULLDOWN)
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{
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__HAL_RTC_PC13_PULL_DOWN_ENABLE();
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}
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}
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if(index->gpio == GPIOC && index->pin == GPIO_PIN_14)
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{
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__HAL_RTC_PC14_DIGIT();
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__HAL_RTC_PC14_SEL(0); /* GPIO function */
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__HAL_RTC_PC14_PULL_DOWN_DISABLE();
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__HAL_RTC_PC14_PULL_UP_DISABLE();
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if(GPIO_InitStruct.Pull == GPIO_PULLUP)
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{
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__HAL_RTC_PC14_PULL_UP_ENABLE();
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}
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else if(GPIO_InitStruct.Pull == GPIO_PULLDOWN)
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{
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__HAL_RTC_PC14_PULL_DOWN_ENABLE();
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}
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}
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if(index->gpio == GPIOC && index->pin == GPIO_PIN_15)
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{
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__HAL_RTC_PC15_DIGIT();
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__HAL_RTC_PC15_SEL(0); /* GPIO function */
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__HAL_RTC_PC15_PULL_DOWN_DISABLE();
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__HAL_RTC_PC15_PULL_UP_DISABLE();
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if(GPIO_InitStruct.Pull == GPIO_PULLUP)
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{
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__HAL_RTC_PC15_PULL_UP_ENABLE();
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}
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else if(GPIO_InitStruct.Pull == GPIO_PULLDOWN)
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{
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__HAL_RTC_PC15_PULL_DOWN_ENABLE();
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}
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}
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2021-08-23 10:13:53 +08:00
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HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
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}
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#define PIN2INDEX(pin) ((pin) % 16)
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2023-04-07 11:42:05 +08:00
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static rt_err_t acm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
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rt_uint8_t mode, void (*hdr)(void *args), void *args)
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2021-08-23 10:13:53 +08:00
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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2023-03-23 13:54:42 +08:00
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return -RT_ENOSYS;
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2021-08-23 10:13:53 +08:00
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}
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irqindex = PIN2INDEX(pin);
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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2023-03-22 03:41:55 +08:00
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return -RT_EBUSY;
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2021-08-23 10:13:53 +08:00
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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2023-04-07 11:42:05 +08:00
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static rt_err_t acm32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
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2021-08-23 10:13:53 +08:00
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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2023-03-23 13:54:42 +08:00
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return -RT_ENOSYS;
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2021-08-23 10:13:53 +08:00
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}
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irqindex = PIN2INDEX(pin);
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t acm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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2023-04-07 11:42:05 +08:00
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rt_uint8_t enabled)
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2021-08-23 10:13:53 +08:00
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{
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const struct pin_index *index;
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struct pin_irq_map *irqmap;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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GPIO_InitTypeDef GPIO_InitStruct;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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2023-03-23 13:54:42 +08:00
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return -RT_ENOSYS;
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2021-08-23 10:13:53 +08:00
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}
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irqindex = PIN2INDEX(pin);
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irqmap = &pin_irq_map[irqindex];
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if (enabled == PIN_IRQ_ENABLE)
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{
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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2023-03-23 13:54:42 +08:00
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return -RT_ENOSYS;
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2021-08-23 10:13:53 +08:00
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}
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2022-03-26 15:40:33 +08:00
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System_Module_Enable(EN_EXTI);
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2021-08-23 10:13:53 +08:00
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/* Configure GPIO_InitStructure */
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GPIO_InitStruct.Pin = index->pin;
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GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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irqmap->handle.u32_Line = irqmap->line;
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irqmap->handle.u32_Mode = EXTI_MODE_INTERRUPT;
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switch (pin_irq_hdr_tab[irqindex].mode)
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{
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case PIN_IRQ_MODE_RISING:
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GPIO_InitStruct.Pull = GPIO_PULLDOWN;
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irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING;
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break;
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case PIN_IRQ_MODE_FALLING:
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GPIO_InitStruct.Pull = GPIO_PULLUP;
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irqmap->handle.u32_Trigger = EXTI_TRIGGER_FALLING;
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING_FALLING;
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break;
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}
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HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
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irqmap->handle.u32_GPIOSel = pin / 16;
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HAL_EXTI_SetConfigLine(&irqmap->handle);
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pin_irq_enable_mask |= 1 << irqindex;
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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if ((pin_irq_enable_mask & (1 << irqindex)) == 0)
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|
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{
|
2023-03-23 13:54:42 +08:00
|
|
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return -RT_ENOSYS;
|
2021-08-23 10:13:53 +08:00
|
|
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}
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level = rt_hw_interrupt_disable();
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EXTI->IENR &= ~irqmap->line;
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EXTI->EENR &= ~irqmap->line;
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rt_hw_interrupt_enable(level);
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}
|
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else
|
|
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|
{
|
|
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|
return -RT_ENOSYS;
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|
|
|
}
|
|
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|
|
return RT_EOK;
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|
}
|
|
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|
|
const static struct rt_pin_ops _acm32_pin_ops =
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|
|
|
{
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|
|
|
acm32_pin_mode,
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|
|
acm32_pin_write,
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|
acm32_pin_read,
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|
|
acm32_pin_attach_irq,
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|
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acm32_pin_dettach_irq,
|
|
|
|
acm32_pin_irq_enable,
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|
|
};
|
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|
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|
|
|
|
rt_inline void pin_irq_hdr(int irqno)
|
|
|
|
{
|
|
|
|
if (pin_irq_hdr_tab[irqno].hdr)
|
|
|
|
{
|
|
|
|
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int rt_hw_pin_init(void)
|
|
|
|
{
|
|
|
|
return rt_device_pin_register("pin", &_acm32_pin_ops, RT_NULL);
|
|
|
|
}
|
|
|
|
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
|
|
|
|
|
|
|
void EXTI_IRQHandler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
for (int i = 0; i < 16; i++)
|
|
|
|
{
|
|
|
|
if (EXTI->PDR & pin_irq_map[i].line)
|
|
|
|
{
|
|
|
|
EXTI->PDR = pin_irq_map[i].line;
|
|
|
|
pin_irq_hdr(i);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* RT_USING_PIN */
|
|
|
|
|