91 lines
3.6 KiB
C
91 lines
3.6 KiB
C
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/*
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* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*!
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* @file buffers.h
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* @definitions for ALL buffer memory space regions used by sdk drivers
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*/
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#define IPU_DEFAULT_WORK_CLOCK 264000000
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#define IPU_DMA_MEMORY_START 0x40000000
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#define IPU_DMA_MEMORY_END 0x43FFFFFF
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#define HDMI_AUDIO_BUF_START 0x4fff0000
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#define HDMI_AUDIO_BUF_END 0x4fff4000
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#define CH23_EBA0 (IPU_DMA_MEMORY_START + 0x00000000)
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#define CH23_EBA1 (IPU_DMA_MEMORY_START + 0x00400000)
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#define CH27_EBA0 (IPU_DMA_MEMORY_START + 0x00800000)
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#define CH27_EBA1 (IPU_DMA_MEMORY_START + 0x00C00000)
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#define CH28_EBA0 (IPU_DMA_MEMORY_START + 0x01000000)
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#define CH28_EBA1 (IPU_DMA_MEMORY_START + 0x01400000)
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#define CH0_EBA0 (IPU_DMA_MEMORY_START + 0x01800000)
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#define CH0_EBA1 (IPU_DMA_MEMORY_START + 0x01C00000)
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/*for dual video playback*/
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#define IPU1_CH23_EBA0 CH23_EBA0
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#define IPU1_CH23_EBA1 CH23_EBA1
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#define IPU2_CH23_EBA0 CH27_EBA0
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#define IPU2_CH23_EBA1 CH27_EBA1
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// for video playback after resizing&rotation
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#define CH22_EBA0 (IPU_DMA_MEMORY_START + 0x01800000)
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#define CH22_EBA1 (IPU_DMA_MEMORY_START + 0x01C00000)
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#define CH21_EBA0 (IPU_DMA_MEMORY_START + 0x02000000)
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#define CH21_EBA1 (IPU_DMA_MEMORY_START + 0x02400000)
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#define CH20_EBA0 (IPU_DMA_MEMORY_START + 0x02800000)
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#define CH20_EBA1 (IPU_DMA_MEMORY_START + 0x02C00000)
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/* put the TWO video instance on different CS to
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improve the performance.
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*/
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#define VPU_WORK_BUFFERS (0x44100000)
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#define VIDEO_BUFFERS_START (0x48000000)
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#define VIDEO_BUFFERS_END (0x4FFFFFFF)
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/*OCRAM partition table*/
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#define VPU_SEC_AXI_START 0x00910000
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#define VPU_SEC_AXI_END 0x0091FFFF
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/* OCRAM ADMA buffer */
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#define USDHC_ADMA_BUFFER1 0x00907000
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#define USDHC_ADMA_BUFFER2 0x00908000
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#define USDHC_ADMA_BUFFER3 0x00909000
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#define USDHC_ADMA_BUFFER4 0x0090A000
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// USB buffers
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#define QH_BUFFER 0x00908000 // internal RAM
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#define TD_BUFFER 0x00908200 // internal RAM
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#define SATA_PROTOCOL_BUFFER_BASE 0x0090a000
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#define SATA_PROTOCOL_BUFFER_SIZE 0x1000
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#define SATA_TRANSFER_BUFFER_BASE 0x0090c000
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