131 lines
3.8 KiB
C
131 lines
3.8 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fwdt_hw.h
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* Date: 2021-08-25 10:27:42
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* LastEditTime: 2022-02-25 11:44:33
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* Description: This files is for ctrl of watchdog timer functions
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 wangxiaodong 2021/8/25 init
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*/
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#ifndef BSP_DRIVERS_FWDT_HW_H
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#define BSP_DRIVERS_FWDT_HW_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "fkernel.h"
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#include "fio.h"
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/* Watchdog register definitions */
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/* refresh frame */
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#define FWDT_GWDT_WRR 0x000
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/* control frame */
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#define FWDT_GWDT_WCS 0x000 /* WCS register */
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#define FWDT_GWDT_WOR 0x008
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#define FWDT_GWDT_WCVL 0x010
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#define FWDT_GWDT_WCVH 0x014
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/* refresh/control frame */
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#define FWDT_GWDT_W_IIDR 0xfcc
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#define FWDT_GWDT_IDR 0xfd0
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/* Watchdog Control and Status Register */
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#define FWDT_GWDT_WCS_WDT_EN BIT(0)
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#define FWDT_GWDT_WCS_WS0 BIT(1)
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#define FWDT_GWDT_WCS_WS1 BIT(2)
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/***************** Macros (Inline Functions) Definitions *********************/
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/**
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* @name: WDT_READ_REG32
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* @msg: read WDT register
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* @param {u32} addr, base address
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* @param {u32} reg_offset, register offset
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* @return {u32} register value
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*/
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#define FWDT_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)(reg_offset))
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/**
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* @name: FWDT_WRITE_REG32
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* @msg: write WDT register
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* @param {u32} addr, base address
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* @param {u32} reg_offset, register offset
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* @param {u32} reg_value, value write to register
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* @return {u32} register value
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*/
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#define FWDT_WRITE_REG32(addr, reg_offset, reg_value) FtOut32((addr) + (u32)(reg_offset), (u32)(reg_value))
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#define FWDT_VERSION_MASK GENMASK(19, 16)
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#define FWDT_CONTINUATION_CODE_MASK GENMASK(11, 8)
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#define FWDT_IDENTIFY_CODE_MASK GENMASK(6, 0)
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/**
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* @name: FWdtReadWCVH
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* @msg: Read wdt wcvh register value. wcvl and wclh register stores the comparison value of the watchdog count.
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* timeout value = comparison value - sys_cnt.
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* @param {uintptr} addr, pointer to a WdtCtrl base addr.
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* @return {u32} register value
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*/
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static inline u32 FWdtReadWCVH(uintptr addr)
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{
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return FWDT_READ_REG32(addr, FWDT_GWDT_WCVH);
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}
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/**
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* @name: FWdtReadWCVL
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* @msg: Read wdt wcvl register value. wcvl and wclh register stores the comparison value of the watchdog count.
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* timeout value = comparison value - sys_cnt.
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* @param {uintptr} addr, pointer to a WdtCtrl base addr.
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* @return {u32} register value
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*/
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static inline u32 FWdtReadWCVL(uintptr addr)
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{
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return FWDT_READ_REG32(addr, FWDT_GWDT_WCVL);
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}
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/**
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* @name: FWdtReadWOR
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* @msg: Read wdt wor register value. used to set timeout value, wor + sys_cnt = wcv.
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* @param {uintptr} addr, pointer to a WdtCtrl base addr.
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* @return {u32} register value
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*/
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static inline u32 FWdtReadWOR(uintptr addr)
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{
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return FWDT_READ_REG32(addr, FWDT_GWDT_WOR);
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}
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/**
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* @name: FWdtReadWCS
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* @msg: Read wdt wcs register value. wcs is control and state register. bit0 enable(1) or disable(0) wdt.
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* @param {uintptr} addr, pointer to a WdtCtrl base addr.
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* @return {u32} register value
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*/
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static inline u32 FWdtReadWCS(uintptr addr)
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{
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return FWDT_READ_REG32(addr, FWDT_GWDT_WCS);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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