164 lines
7.3 KiB
C
164 lines
7.3 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fsata_hw.h
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* Date: 2022-02-10 14:55:11
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* LastEditTime: 2022-02-18 09:03:41
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* Description: This files is for ctrl of sata functions
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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#ifndef BSP_DRIVERS_FSATA_HW_H
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#define BSP_DRIVERS_FSATA_HW_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/***************************** Include Files *********************************/
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#include "fkernel.h"
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#include "ftypes.h"
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#include "fio.h"
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/************************** Constant Definitions *****************************/
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/* SATA register definitions */
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/* Global controller registers */
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#define FSATA_HOST_CAP 0x00 /* host capabilities */
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#define FSATA_HOST_CTL 0x04 /* global host control */
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#define FSATA_HOST_IRQ_STAT 0x08 /* interrupt status */
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#define FSATA_HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
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#define FSATA_HOST_VERSION 0x10 /* AHCI spec. version compliancy */
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#define FSATA_HOST_CAP2 0x24 /* host capabilities, extended */
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/* FSATA_HOST_CTL bits */
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#define FSATA_HOST_CAP_NP_MASK GENMASK(4, 0) /* Number of Ports (NP) */
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#define FSATA_HOST_AHCI_EN BIT(31) /* AHCI enabled */
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#define FSATA_HOST_CAP_SMPS BIT(28) /* AHCI Supports Mechanical Presence Switch */
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#define FSATA_HOST_CAP_SSS BIT(27) /* AHCI staggered spin-up */
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#define FSATA_HOST_CAP_SPM BIT(17) /* AHCI port multiplier */
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#define FSATA_HOST_IRQ_EN BIT(1) /* global IRQ enable */
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#define FSATA_HOST_RESET BIT(0) /* reset controller; self-clear */
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#define FSATA_HOST_PORTS_IMPL_MASK(x) GENMASK(x, 0) /* Ports Implemented */
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/* Registers for each SATA port */
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#define FSATA_PORT_LST_ADDR 0x00 /* command list DMA addr */
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#define FSATA_PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
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#define FSATA_PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
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#define FSATA_PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
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#define FSATA_PORT_IRQ_STAT 0x10 /* interrupt status */
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#define FSATA_PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
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#define FSATA_PORT_CMD 0x18 /* port command */
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#define FSATA_PORT_TFDATA 0x20 /* taskfile data */
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#define FSATA_PORT_SIG 0x24 /* device TF signature */
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#define FSATA_PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
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#define FSATA_PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
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#define FSATA_PORT_SCR_ERR 0x30 /* SATA phy register: SError */
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#define FSATA_PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
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#define FSATA_PORT_CMD_ISSUE 0x38 /* command issue */
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/* PORT_SCR_STAT bits */
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#define FSATA_PORT_SCR_STAT_DET_MASK GENMASK(3, 0)
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#define FSATA_PORT_SCR_STAT_DET_COMINIT 0x1
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#define FSATA_PORT_SCR_STAT_DET_PHYRDY 0x3 /* SATA exist and phy connected */
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/* PORT_CMD bits */
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#define FSATA_PORT_CMD_LIST_ADDR_MASK GENMASK(31, 10)
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#define FSATA_PORT_CMD_FIS_ADDR_MASK GENMASK(31, 8)
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#define FSATA_PORT_CMD_TABLE_ADDR_MASK GENMASK(31, 7)
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#define FSATA_PORT_CMD_ATAPI BIT(24) /* Device is ATAPI */
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#define FSATA_PORT_CMD_LIST_ON BIT(15) /* cmd list DMA engine running */
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#define FSATA_PORT_CMD_FIS_ON BIT(14) /* FIS DMA engine running */
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#define FSATA_PORT_CMD_FIS_RX BIT(4) /* Enable FIS receive DMA engine */
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#define FSATA_PORT_CMD_CLO BIT(3) /* Command list override */
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#define FSATA_PORT_CMD_POWER_ON BIT(2) /* Power up device */
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#define FSATA_PORT_CMD_SPIN_UP BIT(1) /* Spin up device */
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#define FSATA_PORT_CMD_START BIT(0) /* Enable port DMA engine */
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#define FSATA_PORT_CMD_ICC_ACTIVE BIT(28) /* Put i/f in active state */
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#define FSATA_PORT_CMD_ICC_PARTIAL BIT(29) /* Put i/f in partial state */
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#define FSATA_PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
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#define FSATA_PORT_TFDATA_ATA_BUSY BIT(7) /* BSY status bit */
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#define FSATA_PORT_TFDATA_ATA_DRDY BIT(6) /* device ready */
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#define FSATA_PORT_TFDATA_ATA_DF BIT(5) /* device fault */
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#define FSATA_PORT_TFDATA_ATA_DRQ BIT(3) /* data request i/o */
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#define FSATA_PORT_TFDATA_ATA_ERR BIT(0) /* have an error */
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/* PORT_IRQ_{STAT,MASK} bits */
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#define FSATA_PORT_IRQ_COLD_PRES BIT(31) /* cold presence detect */
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#define FSATA_PORT_IRQ_TF_ERR BIT(30) /* task file error */
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#define FSATA_PORT_IRQ_HBUS_ERR BIT(29) /* host bus fatal error */
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#define FSATA_PORT_IRQ_HBUS_DATA_ERR BIT(28) /* host bus data error */
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#define FSATA_PORT_IRQ_IF_ERR BIT(27) /* interface fatal error */
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#define FSATA_PORT_IRQ_IF_NONFATAL BIT(26) /* interface non-fatal error */
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#define FSATA_PORT_IRQ_OVERFLOW BIT(24) /* xfer exhausted available S/G */
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#define FSATA_PORT_IRQ_BAD_PMP BIT(23) /* incorrect port multiplier */
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#define FSATA_PORT_IRQ_PHYRDY BIT(22) /* PhyRdy changed */
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#define FSATA_PORT_IRQ_DEV_ILCK BIT(7) /* device interlock */
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#define FSATA_PORT_IRQ_CONNECT BIT(6) /* port connect change status */
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#define FSATA_PORT_IRQ_SG_DONE BIT(5) /* descriptor processed */
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#define FSATA_PORT_IRQ_UNK_FIS BIT(4) /* unknown FIS rx'd */
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#define FSATA_PORT_IRQ_SDB_FIS BIT(3) /* Set Device Bits FIS rx'd */
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#define FSATA_PORT_IRQ_DMAS_FIS BIT(2) /* DMA Setup FIS rx'd */
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#define FSATA_PORT_IRQ_PIOS_FIS BIT(1) /* PIO Setup FIS rx'd */
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#define FSATA_PORT_IRQ_D2H_REG_FIS BIT(0) /* D2H Register FIS rx'd */
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#define FSATA_PORT_IRQ_FREEZE FSATA_PORT_IRQ_CONNECT | FSATA_PORT_IRQ_SDB_FIS | \
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FSATA_PORT_IRQ_D2H_REG_FIS | FSATA_PORT_IRQ_PIOS_FIS
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#define FSATA_PORT_SCR_ACT_ENABLE BIT(0) /* Port Serial ATA Active */
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#define FSATA_PORT_CMD_ISSUE_ENABLE BIT(0) /* Port Command Issue enable */
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/************************** Variable Definitions *****************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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/**
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* @name: SATA_READ_REG32
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* @msg: 读取SATA寄存器
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* @param {u32} addr 定时器的基地址
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* @param {u32} reg_offset 定时器的寄存器的偏移
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* @return {u32} 寄存器参数
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*/
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#define FSATA_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)reg_offset)
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/**
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* @name: SATA_WRITE_REG32
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* @msg: 写入SATA寄存器
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* @param {u32} addr 定时器的基地址
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* @param {u32} reg_offset 定时器的寄存器的偏移
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* @param {u32} reg_value 写入寄存器参数
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* @return {void}
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*/
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#define FSATA_WRITE_REG32(addr, reg_offset, reg_value) FtOut32((addr) + (u32)reg_offset, (u32)reg_value)
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#define FSATA_SETBIT(base_addr, reg_offset, data) \
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FtSetBit32((base_addr) + (u32)(reg_offset), (u32)(data))
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#define FSATA_CLEARBIT(base_addr, reg_offset, data) \
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FtClearBit32((base_addr) + (u32)(reg_offset), (u32)(data))
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#ifdef __cplusplus
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}
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#endif
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#endif
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