277 lines
9.3 KiB
C
277 lines
9.3 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fsata.h
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* Date: 2022-02-10 14:55:11
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* LastEditTime: 2022-02-18 09:05:24
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* Description: This files is for sata ctrl function definition
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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#ifndef BSP_DRIVERS_FSATA_H
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#define BSP_DRIVERS_FSATA_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/***************************** Include Files *********************************/
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#include "ftypes.h"
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#include "ferror_code.h"
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#include "fkernel.h"
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#define FSATA_SUCCESS FT_SUCCESS
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#define FSATA_ERR_INVAILD_PARAMETER FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 1)
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#define FSATA_ERR_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 2)
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#define FSATA_ERR_OPERATION FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 3)
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#define FSATA_UNKNOWN_DEVICE FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 4)
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/************************** Constant Definitions *****************************/
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#define FSATA_AHCI_MAX_PORTS 32
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#define FSATA_AHCI_MAX_PRD_ENTRIES 16
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#define MAX_DATA_BYTE_COUNT SZ_4M
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#define FSATA_AHCI_CMD_LIST_HEADER_SIZE 0x20
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#define FSATA_AHCI_CMD_LIST_HEADER_NUM 32
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#define FSATA_AHCI_RX_FIS_SZ 0x100
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#define FSATA_AHCI_CMD_TABLE_HEADER_SIZE 0x80
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#define FSATA_AHCI_PRTD_ITEM_SIZE 0x10
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#define FSATA_AHCI_PRTD_ITEM_NUM 0x40 /*set 64 item, hardware max is 64K */
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#define FSATA_AHCI_CMD_TABLE_SIZE (FSATA_AHCI_CMD_TABLE_HEADER_SIZE + (FSATA_AHCI_PRTD_ITEM_NUM * FSATA_AHCI_PRTD_ITEM_SIZE))
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#define FSATA_AHCI_PORT_PRIV_DMA_SZ (FSATA_AHCI_CMD_LIST_HEADER_SIZE * FSATA_AHCI_CMD_LIST_HEADER_NUM + \
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FSATA_AHCI_CMD_TABLE_SIZE + FSATA_AHCI_RX_FIS_SZ)
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#define FSATA_AHCI_CMD_ATAPI BIT(5)
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#define FSATA_AHCI_CMD_WRITE BIT(6)
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#define FSATA_AHCI_CMD_PREFETCH BIT(7)
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#define FSATA_AHCI_CMD_RESET BIT(8)
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#define FSATA_AHCI_CMD_CLR_BUSY BIT(10)
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#define FSATA_ID_LBA48_SECTORS 100
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#define FSATA_ID_LBA_SECTORS 60
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#define FSATA_ID_ATA_DEVICE BIT(15) /* IDENTIFY DEVICE word 0, if ATA device */
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#define FSATA_ID_COMPLETE BIT(2) /* IDENTIFY DEVICE word 0, if the content of the IDENTIFY DEVICE data is incomplete */
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#define FSATA_ID_FW_REV 23 /* firmware revision position */
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#define FSATA_ID_PROD 27 /* Model number position */
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#define FSATA_ID_WORDS 256 /* IDENTIFY DEVICE data length */
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enum
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{
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FSATA_FIS_REG_HOST_TO_DEVICE = 0x27,
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FSATA_FIS_REG_DEVICE_TO_HOST = 0x34,
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FSATA_FIS_DMA_SETUP = 0x41
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};
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#define FSATA_FIS_REG_HOST_TO_DEVICE_C BIT(7) /* update of the command register */
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#define FSATA_CMD_EXT_DEVICE BIT(6) /* command device byte requirement */
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enum
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{
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FSATA_CMD_READ_EXT = 0x25,
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FSATA_CMD_WRITE_EXT = 0x35,
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FSATA_CMD_IDENTIFY_DEVICE = 0xEC,
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FSATA_CMD_FPDMA_READ = 0x60,
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FSATA_CMD_FPDMA_WRITE = 0x61
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};
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#define FSATA_BUSY BIT(7) /* BSY status bit */
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#define FSATA_SECT_SIZE 512 /* sata sector size */
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#define FSATA_BLK_VEN_SIZE 40 /* device vendor string size */
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#define FSATA_BLK_PRD_SIZE 20 /* device product number size */
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#define FSATA_BLK_REV_SIZE 8 /* firmware revision size */
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#define FSATA_DEV_TYPE_UNKNOWN 0xff /* not connected */
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#define FSATA_DEV_TYPE_HARDDISK 0x00 /* harddisk */
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#define FSATA_IF_TYPE_UNKNOWN 0xff
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#define FSATA_IF_TYPE_SCSI 0x00
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enum
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{
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FSATA_TYPE_PCIE = 0,
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FSATA_TYPE_CONTROLLER = 1
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};
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/************************** Variable Definitions *****************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/* Number of User Addressable Logical Sectors lba28 */
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#define FSATA_ID_U32(id,n) \
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(((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
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/* Number of User Addressable Logical Sectors lba48 */
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#define FSATA_ID_U64(id,n) \
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( ((u64) (id)[(n) + 3] << 48) | \
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((u64) (id)[(n) + 2] << 32) | \
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((u64) (id)[(n) + 1] << 16) | \
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((u64) (id)[(n) + 0]) )
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/* if sata id is support lba */
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#define FSataIdHasLba(id) ((id)[49] & BIT(9))
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/* if sata id is support lba48 */
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static inline int FSataIdHasLba48(const u16 *id)
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{
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if ((id[83] & 0xC000) != 0x4000)
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return 0;
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if (!FSATA_ID_U64(id, 100))
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return 0;
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return id[83] & BIT(10);
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}
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/**************************** Type Definitions *******************************/
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typedef void (*FSataIrqCallBack)(void *args);
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/* sata info */
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typedef struct
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{
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unsigned char if_type; /* type of the interface */
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unsigned char type; /* device type */
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char vendor[FSATA_BLK_VEN_SIZE + 1]; /* device vendor string */
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char product[FSATA_BLK_PRD_SIZE + 1]; /* device product number */
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char revision[FSATA_BLK_REV_SIZE + 1]; /* firmware revision */
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unsigned long lba; /* number of blocks */
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unsigned long lba512; /* number of blocks of 512 bytes */
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unsigned long blksz; /* block size */
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} FSataInfo;
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/* Received FIS Structure */
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typedef struct __attribute__((__packed__))
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{
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u8 dma_setup_fis[28];
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u8 reserved0[4];
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u8 pio_setup_fis[20];
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u8 reserved1[12];
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u8 d2h_register_fis[20];
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u8 reserved2[4];
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u8 set_device_bits_fis[8];
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u8 unknown_fis[64];
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u8 reserved3[96];
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}
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FSataAhciRecvFis;
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/* command list structure - command header */
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typedef struct
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{
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u32 description_info;/* DW 0 – Description Information */
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u32 status; /* DW 1 - Command Status */
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u32 tbl_addr; /* DW 2 – Command Table Base Address */
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u32 tbl_addr_hi; /* DW 3 – Command Table Base Address Upper */
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u32 reserved[4];
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} FSataAhciCommandList;
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/* command table - PRDT */
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typedef struct
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{
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u32 addr_low; /* DW 0 – Data Base Address */
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u32 addr_high; /* DW 1 – Data Base Address Upper */
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u32 reserved; /* DW 2 – Reserved */
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u32 data_byte; /* DW 3 – Description Information */
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} FSataAhciCommandTablePrdt;
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/* ahci port information structure */
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typedef struct
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{
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uintptr port_base_addr; /* port base address */
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FSataAhciCommandList *cmd_list; /* Command List structure, will include cmd_tbl's address */
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FSataAhciRecvFis *rx_fis; /* Received FIS Structure */
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uintptr cmd_tbl_base_addr; /* command table addr, also the command table's first part */
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FSataAhciCommandTablePrdt *cmd_tbl_prdt;/* command table's second part , cmd_tbl + cmd_tbl_prdt = command table*/
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FSataInfo dev_info;
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} FSataAhciPorts;
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typedef struct
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{
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u32 instance_id; /* Device instance id */
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uintptr base_addr; /* sata base address */
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char *instance_name; /* instance name */
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u32 irq_num; /* Irq number */
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} FSataConfig; /* sata config */
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typedef struct
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{
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FSataConfig config;
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u32 is_ready;
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FSataAhciPorts port[FSATA_AHCI_MAX_PORTS];
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u16 *ataid[FSATA_AHCI_MAX_PORTS];
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u32 n_ports; /* maximum number of ports supported by the ahci, Number of Ports (NP)*/
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u32 port_map; /* each bit indicate port can be used, If a bit is set to ‘1’, the corresponding port is available for software to use. */
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u32 link_port_map; /* each bit indicate port linkup sata device */
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u32 private_data; /* each bit indicate port sata achi started */
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FSataIrqCallBack fsata_dhrs_cb; /* device-to-host register fis interrupt */
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void *dhrs_args;
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FSataIrqCallBack fsata_pss_cb; /* pio setup fis interrupt */
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void *pss_args;
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FSataIrqCallBack fsata_dss_cb; /* dma setup fis interrupt */
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void *dss_args;
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FSataIrqCallBack fsata_sdbs_cb; /* set device bits interrupt */
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void *sdbs_args;
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FSataIrqCallBack fsata_pcs_cb; /* port connect change status interrupt */
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void *pcs_args;
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volatile u8 dhrs_flag;
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volatile u8 sdb_flag;
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} FSataCtrl;
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/************************** Function Prototypes ******************************/
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/* sata config init */
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const FSataConfig *FSataLookupConfig(u32 instance_id, u8 type);
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/* initialize sata ctrl */
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FError FSataCfgInitialize(FSataCtrl *instance_p, const FSataConfig *input_config_p);
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/* deinitialize sata ctrl */
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void FSataCfgDeInitialize(FSataCtrl *pctrl);
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/* read sata info */
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FError FSataAhciReadInfo(FSataCtrl *instance_p, u8 port);
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/* init ahci */
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FError FSataAhciInit(FSataCtrl *instance_p);
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/* init ahci port */
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FError FSataAhciPortStart(FSataCtrl *instance_p, u8 port, uintptr mem);
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/* read or write sata data */
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FError FSataReadWrite(FSataCtrl *instance_p, u8 port, u32 start,
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u16 blk_cnt, u8 *buffer, boolean is_ncq, boolean is_write);
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/* sata all irq handler entry */
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void FSataIrqHandler(s32 vector, void *param);
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/* set specific sata irq function entry */
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FError FSataSetHandler(FSataCtrl *instance_p, u32 handler_type,
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void *func_pointer, void *call_back_ref);
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/* set sata irq mask */
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void FSataIrqEnable(FSataCtrl *instance_p, u32 int_mask);
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#ifdef __cplusplus
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}
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#endif
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#endif
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