189 lines
7.1 KiB
C
189 lines
7.1 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fqspi_hw.h
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 09:00:23
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* Description: This files is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.1 wangxiaodong 2021.11.12 re-construct
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*/
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#ifndef BSP_DRIVERS_FQSPI_HW_H
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#define BSP_DRIVERS_FQSPI_HW_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "fio.h"
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#include "fkernel.h"
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/* register definition */
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#define FQSPI_REG_CAP_OFFSET (0x00) /* Flash capacity setting register */
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#define FQSPI_REG_RD_CFG_OFFSET (0x04) /* Address access reads configuration registers */
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#define FQSPI_REG_WR_CFG_OFFSET (0x08) /* Write buffer flush register */
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#define FQSPI_REG_FLUSH_OFFSET (0x0C) /* Write buffer flush register */
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#define FQSPI_REG_CMD_PORT_OFFSET (0x10) /* Command port register */
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#define FQSPI_REG_ADDR_PORT_OFFSET (0x14) /* Address port register */
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#define FQSPI_REG_HD_PORT_OFFSET (0x18) /* Upper bit port register */
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#define FQSPI_REG_LD_PORT_OFFSET (0x1C) /* low bit port register */
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#define FQSPI_REG_CS_TIMING_SET_OFFSET (0x20) /* CS setting register */
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#define FQSPI_REG_WIP_RD_OFFSET (0x24) /* WIP reads the Settings register */
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#define FQSPI_REG_WP_OFFSET (0x28) /* WP register */
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#define FQSPI_REG_MODE_OFFSET (0x2C) /* Mode setting register */
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/* FQSPI_CAP */
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#define FQSPI_CAP_FLASH_NUM(data) ((data) << 3) /* Flash number */
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#define FQSPI_CAP_FLASH_CAP(data) ((data) << 0) /* The flash capacity */
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#define FQSPI_CAP_FLASH_NUM_MASK GENMASK(4, 3)
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#define FQSPI_CAP_FLASH_CAP_MASK GENMASK(2, 0)
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/* RD_CFG */
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#define FQSPI_RD_CFG_CMD(data) ((data) << 24) /* Read Command */
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#define FQSPI_RD_CFG_THROUGH(data) ((data) << 23) /* The programming flag in the status register */
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#define FQSPI_RD_CFG_TRANSFER(data) ((data) << 20) /* rd_tranfer region */
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#define FQSPI_RD_CFG_ADDR_SEL(data) ((data) << 19) /* rd_addr_sel region*/
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#define FQSPI_RD_CFG_LATENCY(data) ((data) << 18) /* rd_latency region*/
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#define FQSPI_RD_CFG_MODE_BYTE(data) ((data) << 17) /* mode byte region*/
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#define FQSPI_RD_CFG_CMD_SIGN(data) ((data) << 9) /* cmd_sign region*/
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#define FQSPI_RD_CFG_DUMMY(data) ((data-1) << 4) /* dummy region*/
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#define FQSPI_RD_CFG_D_BUFFER(data) ((data) << 3) /* d_buffer region*/
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#define FQSPI_RD_CFG_SCK_SEL(data) ((data) << 0) /* rd_sck_sel region*/
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#define FQSPI_RD_CFG_CMD_MASK GENMASK(31, 24)
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#define FQSPI_RD_CFG_SCK_SEL_MASK GENMASK(2, 0)
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#define FQSPI_RD_CFG_TRANSFER_MASK GENMASK(22, 20)
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#define FQSPI_RD_CFG_ADDR_SEL_MASK FQSPI_RD_CFG_ADDR_SEL(0x1)
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#define FQSPI_RD_CFG_DUMMY_MASK GENMASK(8, 4)
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/* FQSPI_WR_CFG */
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#define FQSPI_WR_CFG_CMD(data) ((data) << 24)
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#define FQSPI_WR_CFG_WAIT(data) ((data) << 9)
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#define FQSPI_WR_CFG_THROUGH(data) ((data) << 8)
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#define FQSPI_WR_CFG_TRANSFER(data) ((data) << 5)
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#define FQSPI_WR_CFG_ADDRSEL(data) ((data) << 4)
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#define FQSPI_WR_CFG_MODE(data) ((data) << 3)
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#define FQSPI_WR_CFG_SCK_SEL(data) ((data) << 0)
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#define FQSPI_WR_CFG_CMD_MASK GENMASK(31, 24)
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#define FQSPI_WR_CFG_SCK_SEL_MASK GENMASK(2, 0)
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#define FQSPI_WR_CFG_ADDRSEL_MASK FQSPI_WR_CFG_ADDRSEL(0x1)
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/* FQSPI_CMD_PORT */
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#define FQSPI_CMD_PORT_CMD(data) ((data) << 24)
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#define FQSPI_CMD_PORT_WAIT(data) ((data) << 22)
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#define FQSPI_CMD_PORT_THROUGH(data) ((data) << 21)
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#define FQSPI_CMD_PORT_CS(data) ((data) << 19)
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#define FQSPI_CMD_PORT_TRANSFER(data) ((data) << 16)
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#define FQSPI_CMD_PORT_CMD_ADDR(data) ((data) << 15)
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#define FQSPI_CMD_PORT_LATENCY(data) ((data) << 14)
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#define FQSPI_CMD_PORT_DATA_TRANS(data) ((data) << 13)
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#define FQSPI_CMD_PORT_ADDR_SEL(data) ((data) << 12)
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#define FQSPI_CMD_PORT_DUMMY(data) ((data-1) << 7)
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#define FQSPI_CMD_PORT_P_BUFFER(data) ((data) << 6)
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#define FQSPI_CMD_PORT_RW_NUM(data) ((data) << 3)
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#define FQSPI_CMD_PORT_CLK_SEL(data) ((data) << 0)
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#define FQSPI_CMD_PORT_RW_NUM_MASK GENMASK(5, 3)
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#define FQSPI_CMD_PORT_CLK_SEL_MASK GENMASK(2, 0)
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#define FQSPI_CMD_PORT_CS_MASK GENMASK(20, 19)
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#define FQSPI_CMD_PORT_CMD_MASK GENMASK(31, 24)
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#define FQSPI_CMD_PORT_ADDR_SEL_MASK FQSPI_CMD_PORT_ADDR_SEL(0x1)
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#define FQSPI_CMD_PORT_CMD_RW_MAX 8
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/* FQSPI_CS_TIMING_SET */
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#define FQSPI_FUN_SET_CS_HOLD(data) ((data) << 24)
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#define FQSPI_FUN_SET_CS_SETUP(data) ((data) << 16)
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#define FQSPI_FUN_SET_CS_DELAY(data) ((data) << 0)
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/* FQSPI_WIP_RD */
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#define FQSPI_WIP_RD_CMD(data) ((data) << 24)
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#define FQSPI_WIP_RD_TRANSFER(data) ((data) << 3)
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#define FQSPI_WIP_RD_SCK_SEL(data) ((data) << 0)
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/* FQSPI_WP */
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#define FQSPI_WP_EN(data) ((data) << 17)
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#define FQSPI_WP_WP(data) ((data) << 16)
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#define FQSPI_WP_HOLD(data) ((data) << 8)
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#define FQSPI_WP_SETUP(data) ((data) << 0)
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/* FQSPI_MODE */
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#define FQSPI_MODE_VALID(data) ((data) << 8)
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#define FQSPI_MODE_MODE(data) ((data) << 0)
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#define FQSPI_QUAD_READ_MODE_ENABLE 0xF0A0 /* enable FLASH XIP MODE */
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#define FQSPI_QUAD_READ_MODE_DISABLE 0xF0BF /* disable FLASH XIP MODE */
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#define FQSPI_QUAD_READ_MODE_CMD 0xA0 /* FLASH XIP MODE CMD SIGN */
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typedef enum
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{
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FQSPI_CMD_READ = 0x01,
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FQSPI_CMD_WRITE = 0x02,
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} FQspiCmdFlags;
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/**
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* @name: FQSPI_READ_REG32
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* @msg: read FQSPI register
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* @param {u32} addr, base address of FQSPI
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* @param {u32} reg_offset, offset of register
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* @return {u32} register value
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*/
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#define FQSPI_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)(reg_offset))
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/**
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* @name: FQSPI_WRITE_REG32
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* @msg: write FQSPI register
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* @param {u32} addr, base address of FQSPI
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* @param {u32} reg_offset, offset of register
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* @param {u32} reg_value, set register value
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* @return {void}
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*/
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#define FQSPI_WRITE_REG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value)
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/* FQSPI Data Operations */
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#define FQSPI_DAT_WRITE(addr, dat) FtOut32((addr), (u32)(dat))
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/* read ld port data */
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void FQspiGetLdPortData(uintptr base_addr, u8 *buf, size_t len);
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/* set ld port data */
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void FQspiSetLdPortData(uintptr base_addr, const u8 *buf, size_t len);
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/* send command port register config */
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void FQspiCommandPortSend(uintptr base_addr);
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/* address port register config */
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void FQspiAddrPortConfig(uintptr base_addr, u32 addr);
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/* write flush register */
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void FQspiWriteFlush(uintptr base_addr);
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/* qspi xip mode set */
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void FQspiXIPModeSet(uintptr base_addr, u8 enable);
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#ifdef __cplusplus
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}
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#endif
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#endif
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