239 lines
7.1 KiB
C
239 lines
7.1 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fqspi.h
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 09:00:55
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* Description: This files is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.1 wangxiaodong 2021.11.12 re-construct
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*/
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#ifndef BSP_DRIVERS_FQSPI_H
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#define BSP_DRIVERS_FQSPI_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "fkernel.h"
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#include "ftypes.h"
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#include "ferror_code.h"
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#include "fdebug.h"
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#include "fparameters.h"
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#define FQSPI_SUCCESS FT_SUCCESS
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#define FQSPI_INVAL_PARAM FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, 1)
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#define FQSPI_NOT_READY FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, 2)
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#define FQSPI_NOT_ALLIGN FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, 3)
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#define FQSPI_NOT_SUPPORT FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, 4)
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#define FQSPI_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspQSpi, 5)
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/* FQSPI Transfer mode, command-addr-data protocols */
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typedef enum
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{
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FQSPI_TRANSFER_1_1_1 = 0x0,
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FQSPI_TRANSFER_1_1_2 = 0x1,
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FQSPI_TRANSFER_1_1_4 = 0x2,
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FQSPI_TRANSFER_1_2_2 = 0x3,
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FQSPI_TRANSFER_1_4_4 = 0x4,
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FQSPI_TRANSFER_2_2_2 = 0x5,
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FQSPI_TRANSFER_4_4_4 = 0x6
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} FQspiTransferMode;
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/* FQSPI Flash Capcity type */
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typedef enum
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{
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FQSPI_FLASH_CAP_4MB = 0b000,
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FQSPI_FLASH_CAP_8MB = 0b001,
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FQSPI_FLASH_CAP_16MB = 0b010,
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FQSPI_FLASH_CAP_32MB = 0b011,
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FQSPI_FLASH_CAP_64MB = 0b100,
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FQSPI_FLASH_CAP_128MB = 0b101,
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FQSPI_FLASH_CAP_256MB = 0b110,
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} FQspiFlashCapcityType;
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/* FQSPI pclk divider type */
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typedef enum
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{
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FQSPI_SCK_DIV_128 = 0x0,
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FQSPI_SCK_DIV_2 = 0x1,
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FQSPI_SCK_DIV_4 = 0x2,
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FQSPI_SCK_DIV_8 = 0x3,
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FQSPI_SCK_DIV_16 = 0x4,
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FQSPI_SCK_DIV_32 = 0x5,
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FQSPI_SCK_DIV_64 = 0x6
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} FQspiSckDivType;
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/* FQSPI Address type */
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typedef enum
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{
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FQSPI_ADDR_SEL_3 = 0x0,
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FQSPI_ADDR_SEL_4 = 0x1
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} FQspiAddrType;
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/* Specifies if the Instruction need transfer address */
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typedef enum
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{
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FQSPI_CMD_ADDR_DISABLE = 0x0,
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FQSPI_CMD_ADDR_ENABLE = 0x1
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} FQspiCmdAddrType;
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/* Specifies if the Instruction have latency */
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typedef enum
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{
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FQSPI_CMD_LATENCY_DISABLE = 0x0,
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FQSPI_CMD_LATENCY_ENABLE = 0x1
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} FQspiCmdLatencyType;
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/* Specifies if the Instruction need transfer data */
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typedef enum
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{
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FQSPI_CMD_DATA_DISABLE = 0x0,
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FQSPI_CMD_DATA_ENABLE = 0x1
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} FQspiCmdDataType;
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/* Specifies if the Instruction use buffer */
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typedef enum
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{
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FQSPI_USE_BUFFER_DISABLE = 0x0,
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FQSPI_USE_BUFFER_ENABLE = 0x1
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} FQspiUseBufferType;
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/* Specifies if the Instruction need some execution time */
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typedef enum
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{
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FQSPI_WAIT_DISABLE = 0x0,
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FQSPI_WAIT_ENABLE = 0x1
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} FQspiWaitType;
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typedef enum
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{
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FQSPI_XIP_EXIT = 0x0,
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FQSPI_XIP_ENTER = 0x1
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} FQspiXIPState;
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typedef struct
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{
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u32 instance_id; /* Id of device */
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uintptr base_addr; /* Base address of qspi */
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uintptr mem_start; /* Start address of qspi memory */
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u32 capacity; /* Flash capacity */
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u32 dev_num; /* Qspi device number */
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u32 channel; /* channel number, cs number */
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} FQspiConfig;
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/* rd_cfg register */
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typedef struct
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{
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u8 rd_cmd : 8; /* Specifies the Instruction to be sent */
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u8 rd_through : 1;
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u8 rd_transfer : 3;/* Specifies the Instruction tranfer Mode 1-1-1~4-4-4*/
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u8 rd_addr_sel : 1;/* Specifies the Instruction addr mode 3 byte addr or 4 byte addr*/
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u8 rd_latency : 1; /* Specifies if the Instruction need read latency*/
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u8 mode_byte : 1; /* Specifies if the Instruction need modifier*/
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u8 cmd_sign : 8; /* Specifies the Instruction modifier*/
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u8 dummy : 5; /* Specifies the Number of Dummy Cycles.*/
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u8 d_buffer : 1; /* Specifies if the Instruction use buffer to read data*/
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u8 rd_sck_sel : 3; /* Specifies the pclk division .*/
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} FQspiRdCfgDef;
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/* wr_cfg register */
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typedef struct
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{
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u8 wr_cmd : 8; /* Specifies the Instruction to be sent */
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u16 reserved : 14;
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u8 wr_wait : 1;
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u8 wr_through : 1;
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u8 wr_transfer : 3;/* Specifies the Instruction tranfer Mode 1-1-1~4-4-4*/
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u8 wr_addr_sel : 1;/* Specifies the Instruction addr mode 3 byte addr or 4 byte addr*/
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u8 wr_mode : 1; /* Specifies if the Instruction need modifier*/
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u8 wr_sck_sel : 3; /* Specifies the pclk division .*/
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} FQspiWrCfgDef;
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/* cmd_port register */
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typedef struct
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{
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u8 cmd : 8; /* Specifies the Instruction to be sent */
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u8 reserved : 1;
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u8 wait : 1;
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u8 through : 1;
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u8 cs : 2;
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u8 transfer : 3;/* Specifies the Instruction tranfer Mode 1-1-1~4-4-4*/
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u8 cmd_addr : 1; /* Specifies if the Instruction need transfer address*/
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u8 latency : 1; /* Specifies if the Instruction need read latency*/
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u8 data_transfer : 1; /* Specifies if the Instruction need tranfer data*/
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u8 addr_sel : 1; /* Specifies the Instruction addr mode 3 byte addr or 4 byte addr*/
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u8 dummy : 5; /* Specifies the Number of Dummy Cycles.*/
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u8 p_buffer : 1; /* Specifies if the Instruction use buffer to read data*/
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u8 rw_num : 3; /* Specifies the read or write bytes number.*/
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u8 sck_sel : 3; /* Specifies the pclk division .*/
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} FQspiCommandPortDef;
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typedef struct
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{
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u8 cs_hold; /* Specifies the cs valid hold time */
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u8 cs_setup; /* Specifies the cs valid setup time */
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u16 cs_delay; /* Specifies the cs delay time */
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} FQspiCsTimingCfgDef;
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typedef struct
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{
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FQspiConfig config;
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FQspiRdCfgDef rd_cfg;
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FQspiWrCfgDef wr_cfg;
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FQspiCommandPortDef cmd_def;
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FQspiCsTimingCfgDef cs_timing_cfg;
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u32 is_ready; /**< Device is initialized and ready */
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u32 flash_size; /* size of QSPI flash */
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u8 mf_id; /* manufacturer information */
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} FQspiCtrl;
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/* lookup FQSPI default Configuration parameters */
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const FQspiConfig *FQspiLookupConfig(u32 instance_id);
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/* set capacity and number of flash connect to qspi */
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void FQspiSetCapacityAndNum(FQspiCtrl *pctrl);
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/* qspi instance initialization */
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FError FQspiCfgInitialize(FQspiCtrl *pctrl, const FQspiConfig *input_config_p);
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/* qspi instance de-initialization */
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void FQspiDeInitialize(FQspiCtrl *pctrl);
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/* command port register config */
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FError FQspiCommandPortConfig(FQspiCtrl *pctrl);
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/* read register config */
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FError FQspiRdCfgConfig(FQspiCtrl *pctrl);
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/* write register config */
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FError FQspiWrCfgConfig(FQspiCtrl *pctrl);
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/* qspi cs number set */
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void FQspiChannelSet(FQspiCtrl *pctrl, FQspiChipCS channel);
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/* qspi cs timing set */
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void FQspiCsTimingSet(FQspiCtrl *pctrl, FQspiCsTimingCfgDef *cs_timing_cfg);
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#ifdef __cplusplus
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}
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#endif
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#endif
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