468 lines
15 KiB
C
468 lines
15 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fnand_timing.c
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* Date: 2022-05-09 14:53:42
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* LastEditTime: 2022-05-09 08:56:27
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* Description: This files is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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#include "ferror_code.h"
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#include "fnand.h"
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#include "fnand_hw.h"
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#include "fdebug.h"
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#define FNAND_TIMING_DEBUG_TAG "FNAND_TIMING"
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#define FNAND_TIMING_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FNAND_TIMING_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FNAND_TIMING_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FNAND_TIMING_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FNAND_TIMING_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FNAND_TIMING_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FNAND_TIMING_ASY_NUM 12
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#define FNAND_TIMING_SYN_NUM 14
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#define FNAND_TIMING_TOG_NUM 12
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const u16 fnand_timing_asy_mode0[FNAND_TIMING_ASY_NUM] = {0x03, 0x03, 0x28, 0x28, 0x03, 0x03, 0x06, 0x06, 0x28, 0x70, 0x30, 0x50};
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const u16 fnand_timing_asy_mode1[FNAND_TIMING_ASY_NUM] = {0x03, 0x03, 0x14, 0x14, 0x03, 0x03, 0x06, 0x06, 0x14, 0x70, 0x20, 0x28};
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const u16 fnand_timing_asy_mode2[FNAND_TIMING_ASY_NUM] = {0x03, 0x03, 0x0D, 0x0D, 0x03, 0x03, 0x06, 0x06, 0x0D, 0x70, 0x20, 0x1A};
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const u16 fnand_timing_asy_mode3[FNAND_TIMING_ASY_NUM] = {0x03, 0x03, 0x0A, 0x0A, 0x03, 0x03, 0x06, 0x06, 0x0A, 0x70, 0x20, 0x14};
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const u16 fnand_timing_asy_mode4[FNAND_TIMING_ASY_NUM] = {0x03, 0x03, 0x08, 0x08, 0x03, 0x03, 0x06, 0x06, 0x08, 0x70, 0x15, 0x10};
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const u16 fnand_timing_asy_mode5[FNAND_TIMING_ASY_NUM] = {0x03, 0x03, 0x07, 0x07, 0x03, 0x03, 0x06, 0x06, 0x07, 0x20, 0x15, 0x0E};
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const u16 fnand_timing_syn_mode0[FNAND_TIMING_SYN_NUM] = {0x20, 0x41, 0x05, 0x20, 0x10, 0x19, 0x62, 0x40, 0x38, 0x20, 0x00, 0x09, 0x50, 0x20};
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const u16 fnand_timing_syn_mode1[FNAND_TIMING_SYN_NUM] = {0x18, 0x32, 0x06, 0x18, 0x0C, 0x10, 0x76, 0x40, 0x2A, 0x18, 0x00, 0x12, 0x24, 0x18};
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const u16 fnand_timing_syn_mode2[FNAND_TIMING_SYN_NUM] = {0x10, 0x0A, 0x04, 0x10, 0x08, 0x0A, 0x6E, 0x50, 0x1D, 0x10, 0x00, 0x0C, 0x18, 0x10};
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const u16 fnand_timing_syn_mode3[FNAND_TIMING_SYN_NUM] = {0x0C, 0x1A, 0x02, 0x0C, 0x06, 0x08, 0x78, 0x7C, 0x15, 0x0C, 0x00, 0x08, 0x12, 0x0C};
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const u16 fnand_timing_syn_mode4[FNAND_TIMING_SYN_NUM] = {0x08, 0x17, 0x05, 0x08, 0x04, 0x01, 0x73, 0x40, 0x0C, 0x08, 0x00, 0x06, 0x0C, 0x10};
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const u16 fnand_timing_tog_ddr_mode0[FNAND_TIMING_TOG_NUM] = {0x14, 0x0a, 0x08, 0x08, 0xc8, 0xc8, 0x08, 0x08, 0x14, 0x0a, 0x14, 0x08}; /* 600M clk */
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#define ONFI_DYN_TIMING_MAX ((u16)~0U)
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static const struct FNandSdrTimings onfi_sdr_timings[] =
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{
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{
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 20000,
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.tALS_min = 50000,
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.tAR_min = 25000,
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.tCEA_max = 100000,
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.tCEH_min = 20000,
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.tCH_min = 20000,
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.tCHZ_max = 100000,
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.tCLH_min = 20000,
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.tCLR_min = 20000,
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.tCLS_min = 50000,
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.tCOH_min = 0,
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.tCS_min = 70000,
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.tDH_min = 20000,
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.tDS_min = 40000,
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.tFEAT_max = 1000000,
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.tIR_min = 10000,
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.tITC_max = 1000000,
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.tRC_min = 100000,
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.tREA_max = 40000,
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.tREH_min = 30000,
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.tRHOH_min = 0,
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.tRHW_min = 200000,
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.tRHZ_max = 200000,
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.tRLOH_min = 0,
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.tRP_min = 50000,
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.tRR_min = 40000,
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.tRST_max = 250000000000ULL,
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.tWB_max = 200000,
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.tWC_min = 100000,
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.tWH_min = 30000,
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.tWHR_min = 120000,
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.tWP_min = 50000,
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.tWW_min = 100000,
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},
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/* Mode 1 */
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{
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 10000,
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.tALS_min = 25000,
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.tAR_min = 10000,
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.tCEA_max = 45000,
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.tCEH_min = 20000,
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.tCH_min = 10000,
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.tCHZ_max = 50000,
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.tCLH_min = 10000,
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.tCLR_min = 10000,
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.tCLS_min = 25000,
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.tCOH_min = 15000,
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.tCS_min = 35000,
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.tDH_min = 10000,
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.tDS_min = 20000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 50000,
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.tREA_max = 30000,
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.tREH_min = 15000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 0,
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.tRP_min = 25000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 45000,
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.tWH_min = 15000,
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.tWHR_min = 80000,
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.tWP_min = 25000,
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.tWW_min = 100000,
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},
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/* Mode 2 */
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{
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 10000,
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.tALS_min = 15000,
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.tAR_min = 10000,
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.tCEA_max = 30000,
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.tCEH_min = 20000,
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.tCH_min = 10000,
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.tCHZ_max = 50000,
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.tCLH_min = 10000,
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.tCLR_min = 10000,
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.tCLS_min = 15000,
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.tCOH_min = 15000,
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.tCS_min = 25000,
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.tDH_min = 5000,
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.tDS_min = 15000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 35000,
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.tREA_max = 25000,
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.tREH_min = 15000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 0,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tRP_min = 17000,
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.tWC_min = 35000,
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.tWH_min = 15000,
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.tWHR_min = 80000,
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.tWP_min = 17000,
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.tWW_min = 100000,
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},
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/* Mode 3 */
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{
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 5000,
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.tALS_min = 10000,
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.tAR_min = 10000,
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.tCEA_max = 25000,
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.tCEH_min = 20000,
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.tCH_min = 5000,
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.tCHZ_max = 50000,
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.tCLH_min = 5000,
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.tCLR_min = 10000,
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.tCLS_min = 10000,
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.tCOH_min = 15000,
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.tCS_min = 25000,
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.tDH_min = 5000,
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.tDS_min = 10000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 30000,
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.tREA_max = 20000,
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.tREH_min = 10000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 0,
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.tRP_min = 15000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 30000,
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.tWH_min = 10000,
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.tWHR_min = 80000,
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.tWP_min = 15000,
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.tWW_min = 100000,
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},
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/* Mode 4 */
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{
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 5000,
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.tALS_min = 10000,
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.tAR_min = 10000,
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.tCEA_max = 25000,
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.tCEH_min = 20000,
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.tCH_min = 5000,
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.tCHZ_max = 30000,
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.tCLH_min = 5000,
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.tCLR_min = 10000,
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.tCLS_min = 10000,
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.tCOH_min = 15000,
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.tCS_min = 20000,
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.tDH_min = 5000,
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.tDS_min = 10000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 25000,
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.tREA_max = 20000,
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.tREH_min = 10000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 5000,
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.tRP_min = 12000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 25000,
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.tWH_min = 10000,
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.tWHR_min = 80000,
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.tWP_min = 12000,
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.tWW_min = 100000,
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},
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/* Mode 5 */
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{
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 5000,
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.tALS_min = 10000,
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.tAR_min = 10000,
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.tCEA_max = 25000,
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.tCEH_min = 20000,
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.tCH_min = 5000,
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.tCHZ_max = 30000,
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.tCLH_min = 5000,
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.tCLR_min = 10000,
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.tCLS_min = 10000,
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.tCOH_min = 15000,
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.tCS_min = 15000,
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.tDH_min = 5000,
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.tDS_min = 7000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 20000,
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.tREA_max = 16000,
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.tREH_min = 7000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 5000,
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.tRP_min = 10000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 20000,
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.tWH_min = 7000,
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.tWHR_min = 80000,
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.tWP_min = 10000,
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.tWW_min = 100000,
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},
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};
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static FError FNandMemcpyToReg16(FNand *instance_p, u32 reg, u32 reg_step, const u16 *buf, u32 len)
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{
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u32 i;
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u32 value = 0;
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if (!instance_p || !buf)
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{
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FNAND_TIMING_DEBUG_E("instance_p is %p ,buf is %p", instance_p, buf);
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return FNAND_ERR_INVAILD_PARAMETER;
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}
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for (i = 0; i < len; i++)
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{
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value = (value << 16) + buf[i];
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|||
|
|
if (i % 2)
|
|||
|
|
{
|
|||
|
|
FNAND_WRITEREG(instance_p->config.base_address, reg, value);
|
|||
|
|
value = 0;
|
|||
|
|
reg += reg_step;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return FT_SUCCESS;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name:
|
|||
|
|
* @msg: 根据inter_mode 与 timing_mode
|
|||
|
|
* @note:
|
|||
|
|
* @return {*}
|
|||
|
|
* @param {FNand} *instance_p
|
|||
|
|
*/
|
|||
|
|
FError FNandTimingInterfaceUpdate(FNand *instance_p, u32 chip_addr)
|
|||
|
|
{
|
|||
|
|
FASSERT(instance_p != NULL);
|
|||
|
|
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
|
|||
|
|
FASSERT(chip_addr < FNAND_CONNECT_MAX_NUM);
|
|||
|
|
const u16 *target_timming_data = NULL;
|
|||
|
|
FNandConfig *config_p = &instance_p->config ;
|
|||
|
|
u32 value = 0 ;
|
|||
|
|
FError ret;
|
|||
|
|
|
|||
|
|
FNandSetOption(instance_p, FNAND_OPS_INTER_MODE_SELECT, instance_p->inter_mode[chip_addr]);
|
|||
|
|
|
|||
|
|
FNAND_CLEARBIT(config_p->base_address, FNAND_CTRL1_OFFSET, FNAND_CTRL1_SAMPL_PHASE_MAKE(0xffffUL)); /* clear sampl_phase */
|
|||
|
|
switch (instance_p->inter_mode[chip_addr])
|
|||
|
|
{
|
|||
|
|
case FNAND_ASYN_SDR:
|
|||
|
|
if (FNAND_TIMING_MODE4 == (instance_p->timing_mode[chip_addr] & 0xf))
|
|||
|
|
{
|
|||
|
|
target_timming_data = fnand_timing_asy_mode4;
|
|||
|
|
value = FNAND_CTRL1_SAMPL_PHASE_MAKE(4UL) ;
|
|||
|
|
}
|
|||
|
|
else if (FNAND_TIMING_MODE3 == (instance_p->timing_mode[chip_addr] & 0xf))
|
|||
|
|
{
|
|||
|
|
target_timming_data = fnand_timing_asy_mode3;
|
|||
|
|
value = FNAND_CTRL1_SAMPL_PHASE_MAKE(5UL) ;
|
|||
|
|
}
|
|||
|
|
else if (FNAND_TIMING_MODE2 == (instance_p->timing_mode[chip_addr] & 0xf))
|
|||
|
|
{
|
|||
|
|
target_timming_data = fnand_timing_asy_mode2;
|
|||
|
|
value = FNAND_CTRL1_SAMPL_PHASE_MAKE(6UL) ;
|
|||
|
|
}
|
|||
|
|
else if (FNAND_TIMING_MODE1 == (instance_p->timing_mode[chip_addr] & 0xf))
|
|||
|
|
{
|
|||
|
|
target_timming_data = fnand_timing_asy_mode1;
|
|||
|
|
value = FNAND_CTRL1_SAMPL_PHASE_MAKE(5UL) ;
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
target_timming_data = fnand_timing_asy_mode0;
|
|||
|
|
value = FNAND_CTRL1_SAMPL_PHASE_MAKE(1UL) ;
|
|||
|
|
}
|
|||
|
|
ret = FNandMemcpyToReg16(instance_p, FNAND_ASY_TIMING0_OFFSET, 4, target_timming_data, FNAND_TIMING_ASY_NUM);
|
|||
|
|
if (ret != FT_SUCCESS)
|
|||
|
|
{
|
|||
|
|
return ret;
|
|||
|
|
}
|
|||
|
|
FNAND_SETBIT(config_p->base_address, FNAND_CTRL1_OFFSET, value);
|
|||
|
|
FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 1);
|
|||
|
|
break;
|
|||
|
|
case FNAND_ONFI_DDR:
|
|||
|
|
if (FNAND_TIMING_MODE4 == (instance_p->timing_mode[chip_addr] & 0xf))
|
|||
|
|
{
|
|||
|
|
FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x30);
|
|||
|
|
target_timming_data = fnand_timing_syn_mode4;
|
|||
|
|
value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0xdUL) ;
|
|||
|
|
}
|
|||
|
|
else if (FNAND_TIMING_MODE3 == (instance_p->timing_mode[chip_addr] & 0xf))
|
|||
|
|
{
|
|||
|
|
FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x18);
|
|||
|
|
target_timming_data = fnand_timing_syn_mode3;
|
|||
|
|
value = FNAND_CTRL1_SAMPL_PHASE_MAKE(5UL) ;
|
|||
|
|
}
|
|||
|
|
else if (FNAND_TIMING_MODE2 == (instance_p->timing_mode[chip_addr] & 0xf))
|
|||
|
|
{
|
|||
|
|
FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x20);
|
|||
|
|
target_timming_data = fnand_timing_syn_mode2;
|
|||
|
|
value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0x8UL) ;
|
|||
|
|
}
|
|||
|
|
else if (FNAND_TIMING_MODE1 == (instance_p->timing_mode[chip_addr] & 0xf))
|
|||
|
|
{
|
|||
|
|
FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x40);
|
|||
|
|
target_timming_data = fnand_timing_syn_mode1;
|
|||
|
|
value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0x12UL) ;
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x40);
|
|||
|
|
target_timming_data = fnand_timing_syn_mode0;
|
|||
|
|
value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0x12UL) ;
|
|||
|
|
}
|
|||
|
|
ret = FNandMemcpyToReg16(instance_p, FNAND_SYN_TIMING6_OFFSET, 4, target_timming_data, FNAND_TIMING_SYN_NUM);
|
|||
|
|
if (ret != FT_SUCCESS)
|
|||
|
|
{
|
|||
|
|
return ret;
|
|||
|
|
}
|
|||
|
|
FNAND_SETBIT(config_p->base_address, FNAND_CTRL1_OFFSET, value);
|
|||
|
|
break;
|
|||
|
|
case FNAND_TOG_ASYN_DDR:
|
|||
|
|
value = FNAND_CTRL1_SAMPL_PHASE_MAKE(8UL);
|
|||
|
|
target_timming_data = fnand_timing_tog_ddr_mode0;
|
|||
|
|
ret = FNandMemcpyToReg16(instance_p, FNAND_TOG_TIMING13_OFFSET, 4, target_timming_data, FNAND_TIMING_SYN_NUM);
|
|||
|
|
if (ret != FT_SUCCESS)
|
|||
|
|
{
|
|||
|
|
return ret;
|
|||
|
|
}
|
|||
|
|
FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0xc8);
|
|||
|
|
FNAND_SETBIT(config_p->base_address, FNAND_CTRL1_OFFSET, value);
|
|||
|
|
break;
|
|||
|
|
default:
|
|||
|
|
FNAND_TIMING_DEBUG_E("Error inter_mode is %x", instance_p->inter_mode[chip_addr]);
|
|||
|
|
return FNAND_ERR_INVAILD_PARAMETER;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return FT_SUCCESS;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
const struct FNandSdrTimings *FNandAsyncTimingModeToSdrTimings(FNandAsyncTimint mode)
|
|||
|
|
{
|
|||
|
|
if (mode >= FNAND_ASYNC_TIM_INT_MODE4)
|
|||
|
|
{
|
|||
|
|
FNAND_TIMING_DEBUG_E("FNandAsyncTimingModeToSdrTimings set is over mode range");
|
|||
|
|
return NULL;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return &onfi_sdr_timings[mode];
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name:
|
|||
|
|
* @msg:
|
|||
|
|
* @return {*}
|
|||
|
|
* @param {FNand} *instance_p
|
|||
|
|
* @param {FNandAsyncTimint} mode
|
|||
|
|
* @Note 当前只支持onfi 模式
|
|||
|
|
*/
|
|||
|
|
FError FNandFillTimingModeTiming(FNand *instance_p, FNandAsyncTimint mode)
|
|||
|
|
{
|
|||
|
|
struct FNandSdrTimings *sdr_timing_p = NULL;
|
|||
|
|
const struct FNandSdrTimings *source_timing_p = NULL;
|
|||
|
|
FASSERT(instance_p != NULL);
|
|||
|
|
sdr_timing_p = &instance_p->sdr_timing;
|
|||
|
|
source_timing_p = FNandAsyncTimingModeToSdrTimings(mode);
|
|||
|
|
FASSERT(source_timing_p != NULL);
|
|||
|
|
*sdr_timing_p = *source_timing_p;
|
|||
|
|
|
|||
|
|
|
|||
|
|
return FT_SUCCESS;
|
|||
|
|
}
|