433 lines
12 KiB
C
433 lines
12 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fi2c_hw.c
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 08:36:22
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* Description: This files is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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/***************************** Include Files *********************************/
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#include <string.h>
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#include "fsleep.h"
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#include "fdebug.h"
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#include "ferror_code.h"
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#include "fassert.h"
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#include "fi2c_hw.h"
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#include "fi2c.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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typedef struct
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{
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u32 speed_mode;
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u32 scl_lcnt;
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u32 scl_hcnt;
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u32 sda_hold;
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} FI2cSpeedCfg; /* speed related configs */
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typedef struct
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{
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u32 speed;
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u32 min_scl_hightime_ns;
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u32 min_scl_lowtime_ns;
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u32 def_risetime_ns;
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u32 def_falltime_ns;
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} FI2cSpeedModeInfo; /* speed calculation related configs */
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/************************** Variable Definitions *****************************/
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static const FI2cSpeedModeInfo I2C_SPEED_CFG[FI2C_SPEED_MODE_MAX] =
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{
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[FI2C_STANDARD_SPEED] = {
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FI2C_SPEED_STANDARD_RATE,
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4000,
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4700,
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1000,
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300,
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},
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[FI2C_FAST_SPEED] = {
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FI2C_SPEED_FAST_RATE,
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1000,
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1300,
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300,
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300,
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}
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};
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FI2C_DEBUG_TAG "I2C_HW"
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#define FI2C_ERROR(format, ...) FT_DEBUG_PRINT_E(FI2C_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FI2C_INFO(format, ...) FT_DEBUG_PRINT_I(FI2C_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FI2C_DEBUG(format, ...) FT_DEBUG_PRINT_D(FI2C_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FI2C_TIMEOUT 500
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/************************** Function Prototypes ******************************/
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/**
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* @name: FI2cSetEnable
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* @msg: 设置I2C控制器的使能状态
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* @return {*}
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* @param {uintptr} addr， I2c控制器基地址
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* @param {boolean} enable， TRUE: 使能，FALSE: 去使能
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*/
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FError FI2cSetEnable(uintptr addr, boolean enable)
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{
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u32 status = enable ? FI2C_IC_ENABLE : FI2C_IC_DISABLE;
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u32 timeout = FI2C_TIMEOUT;
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do
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{
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FI2C_WRITE_REG32(addr, FI2C_ENABLE_OFFSET, status);
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if (((FI2C_READ_REG32(addr, FI2C_ENABLE_STATUS_OFFSET)) & FI2C_IC_ENABLE_MASK) == status)
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{
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return FI2C_SUCCESS;
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}
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}
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while (0 != timeout--);
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FI2C_ERROR("timeout in %sabling I2C ctrl", enable ? "en" : "dis");
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return FI2C_ERR_TIMEOUT;
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}
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/**
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* @name: FI2cCalcTiming
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* @msg: 计算I2C的上升沿下降沿配置
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* @return {*}
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* @param {u32} bus_clk_hz， I2C总线时钟速度 Hz，默认48MHz
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* @param {u32} spk_cnt, spk数目
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* @param {FI2cSpeedCfg} *speed_cfg_p，速度配置
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*/
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static FError FI2cCalcTiming(u32 bus_clk_hz, u32 spk_cnt, FI2cSpeedCfg *speed_cfg_p)
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{
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FASSERT(speed_cfg_p);
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u32 speed_mode = speed_cfg_p->speed_mode;
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const FI2cSpeedModeInfo *info_p = &I2C_SPEED_CFG[speed_mode];
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int fall_cnt, rise_cnt, min_t_low_cnt, min_t_high_cnt;
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int hcnt, lcnt, period_cnt, diff, tot;
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int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
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period_cnt = bus_clk_hz / info_p->speed;
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scl_rise_time_ns = info_p->def_risetime_ns;
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scl_fall_time_ns = info_p->def_falltime_ns;
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/* convert a period to a number of IC clk cycles */
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rise_cnt = DIV_ROUND_UP(bus_clk_hz / 1000 * scl_rise_time_ns, NANO_TO_KILO);
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fall_cnt = DIV_ROUND_UP(bus_clk_hz / 1000 * scl_fall_time_ns, NANO_TO_KILO);
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min_t_low_cnt = DIV_ROUND_UP(bus_clk_hz / 1000 * info_p->min_scl_lowtime_ns, NANO_TO_KILO);
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min_t_high_cnt = DIV_ROUND_UP(bus_clk_hz / 1000 * info_p->min_scl_hightime_ns, NANO_TO_KILO);
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FI2C_INFO("i2c: mode %d, bus_clk %d, speed %d, period %d rise %d fall %d tlow %d thigh %d spk %d\n",
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speed_mode, bus_clk_hz, info_p->speed, period_cnt, rise_cnt, fall_cnt,
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min_t_low_cnt, min_t_high_cnt, spk_cnt);
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/*
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* Back-solve for hcnt and lcnt according to the following equations:
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* SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * icClk] + SCL_Fall_time
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* SCL_Low_time = [(LCNT + 1) * icClk] - SCL_Fall_time + SCL_Rise_time
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*/
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hcnt = min_t_high_cnt - fall_cnt - 7 - spk_cnt;
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lcnt = min_t_low_cnt - rise_cnt + fall_cnt - 1;
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if (hcnt < 0 || lcnt < 0)
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{
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FI2C_ERROR("i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
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return FI2C_ERR_INVAL_PARM;
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}
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/*
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* Now add things back up to ensure the period is hit. If it is off,
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* split the difference and bias to lcnt for remainder
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*/
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tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
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if (tot < period_cnt)
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{
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diff = (period_cnt - tot) / 2;
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hcnt += diff;
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lcnt += diff;
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tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
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lcnt += period_cnt - tot;
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}
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speed_cfg_p->scl_lcnt = lcnt;
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speed_cfg_p->scl_hcnt = hcnt;
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speed_cfg_p->sda_hold = DIV_ROUND_UP(bus_clk_hz / 1000 * 300, NANO_TO_KILO); /* Use internal default unless other value is specified */
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FI2C_INFO("i2c: hcnt = %d lcnt = %d sda hold = %d\n",
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speed_cfg_p->scl_hcnt,
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speed_cfg_p->scl_lcnt,
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speed_cfg_p->sda_hold);
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return FI2C_SUCCESS;
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}
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/**
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* @name: FI2cCalcSpeedCfg
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* @msg: 计算I2C的速度配置
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* @return {*}
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* @param {uintptr} addr, I2C控制器基地址
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* @param {u32} speed, I2C传输速率
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* @param {u32} bus_clk_hz, I2C时钟频率
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* @param {FI2cSpeedCfg} *speed_cfg_p, I2C速度配置
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*/
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static FError FI2cCalcSpeedCfg(uintptr addr, u32 speed, u32 bus_clk_hz, FI2cSpeedCfg *speed_cfg_p)
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{
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FASSERT(speed_cfg_p);
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u32 spk_cnt = 0;
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if (FI2C_SPEED_FAST_RATE <= speed)
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speed_cfg_p->speed_mode = FI2C_FAST_SPEED;
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else if (FI2C_SPEED_STANDARD_RATE <= speed)
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speed_cfg_p->speed_mode = FI2C_STANDARD_SPEED;
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else
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return FI2C_ERR_INVAL_PARM;
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spk_cnt = FI2C_READ_REG32(addr, FI2C_FS_SPKLEN_OFFSET);
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return FI2cCalcTiming(bus_clk_hz, spk_cnt, speed_cfg_p);
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}
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/**
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* @name: FI2cSetSpeed
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* @msg: 设置I2C控制器的速率
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* @return {*}
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* @param {uintptr} addr, I2C控制器基地址
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* @param {u32} speed_rate, I2C传输速率
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*/
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FError FI2cSetSpeed(uintptr addr, u32 speed_rate)
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{
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FError ret = FI2C_SUCCESS;
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FI2cSpeedCfg speed_cfg;
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u32 enable_status;
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u32 reg_val;
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memset(&speed_cfg, 0, sizeof(speed_cfg));
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ret = FI2cCalcSpeedCfg(addr, speed_rate, I2C_REF_CLK_HZ, &speed_cfg);
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if (FI2C_SUCCESS != ret)
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return ret;
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/* get enable setting for restore later */
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enable_status = FI2cGetEnable(addr);
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/* reset speed mode bits */
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reg_val = ((FI2C_READ_REG32(addr, FI2C_CON_OFFSET)) & (~FI2C_CON_SPEED_MASK));
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switch (speed_cfg.speed_mode)
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{
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case FI2C_STANDARD_SPEED:
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reg_val |= FI2C_CON_STD_SPEED;
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FI2C_WRITE_REG32(addr, FI2C_SS_SCL_HCNT_OFFSET, speed_cfg.scl_hcnt);
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FI2C_WRITE_REG32(addr, FI2C_SS_SCL_LCNT_OFFSET, speed_cfg.scl_lcnt);
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break;
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case FI2C_FAST_SPEED:
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reg_val |= FI2C_CON_FAST_SPEED;
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FI2C_WRITE_REG32(addr, FI2C_FS_SCL_HCNT_OFFSET, speed_cfg.scl_hcnt);
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FI2C_WRITE_REG32(addr, FI2C_FS_SCL_LCNT_OFFSET, speed_cfg.scl_lcnt);
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break;
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default:
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ret |= FI2C_ERR_INVAL_PARM;
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break;
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}
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FI2C_WRITE_REG32(addr, FI2C_CON_OFFSET, reg_val);
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/* Configure SDA Hold Time if required */
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if (0 != speed_cfg.sda_hold)
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FI2C_WRITE_REG32(addr, FI2C_SDA_HOLD_OFFSET, speed_cfg.sda_hold);
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/* Restore back i2c now speed set */
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if (FI2C_IC_ENABLE == enable_status)
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{
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ret |= FI2cSetEnable(addr, TRUE);
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}
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return ret;
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}
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/**
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* @name: FI2cWaitStatus
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* @msg: 等待特定的I2C状态位直到状态不存在或者超时
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* @return {*}
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* @param {uintptr} addr, I2C控制器基地址
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* @param {u32} stat_bit, I2C状态位
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*/
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FError FI2cWaitStatus(uintptr addr, u32 stat_bit)
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{
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u32 timeout = 0;
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/* wait until statbit was set or timeout */
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do
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{
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fsleep_millisec(2); /*wait 2 ms*/
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}
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while (!((FI2C_READ_REG32(addr, FI2C_STATUS_OFFSET)) & stat_bit) && (FI2C_TIMEOUT > ++timeout));
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if (FI2C_TIMEOUT <= timeout)
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{
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FI2C_ERROR("timeout when wait status: 0x%x", stat_bit);
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return FI2C_ERR_TIMEOUT;
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}
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return FI2C_SUCCESS;
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}
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/**
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* @name: FI2cWaitBusBusy
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* @msg: 等待I2C总线忙
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* @return {*}
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* @param {uintptr} addr, I2C控制器基地址
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*/
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FError FI2cWaitBusBusy(uintptr addr)
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{
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u32 timeout = FI2C_TIMEOUT;
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u32 ret = FI2C_SUCCESS;
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if (((FI2C_READ_REG32(addr, FI2C_STATUS_OFFSET)) & FI2C_STATUS_MST_ACTIVITY) &&
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(FI2C_SUCCESS != FI2cWaitStatus(addr, FI2C_STATUS_TFE)))
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{
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ret = FI2C_ERR_TIMEOUT;
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FI2C_ERROR("timeout when wait i2c bus busy");
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}
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return ret;
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}
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/**
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* @name: FI2cSetTar
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* @msg: 设置与I2C主机通信的从机地址
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* @return {*}
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* @param {uintptr} addr, I2C控制器基地址
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* @param {u32} tar_addr, I2C从机地址
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*/
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FError FI2cSetTar(uintptr addr, u32 tar_addr)
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{
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u32 enable_status = FI2cGetEnable(addr);
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u32 ret = FI2C_SUCCESS;
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u32 reg_val = 0;
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|||
|
|
|
|||
|
|
if (FI2C_IC_ENABLE == enable_status)
|
|||
|
|
ret = FI2cSetEnable(addr, FALSE);
|
|||
|
|
|
|||
|
|
if (FI2C_SUCCESS == ret)
|
|||
|
|
FI2C_WRITE_REG32(addr, FI2C_TAR_OFFSET, (tar_addr & FI2C_IC_TAR_MASK));
|
|||
|
|
|
|||
|
|
if (FI2C_IC_ENABLE == enable_status)
|
|||
|
|
ret = FI2cSetEnable(addr, TRUE);
|
|||
|
|
|
|||
|
|
return ret;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FI2cSetSar
|
|||
|
|
* @msg: 从机模式下，设置I2C地址
|
|||
|
|
* @return {*}
|
|||
|
|
* @param {uintptr} addr, I2C控制器基地址
|
|||
|
|
* @param {u32} sar_addr, 作为从机的地址
|
|||
|
|
*/
|
|||
|
|
FError FI2cSetSar(uintptr addr, u32 sar_addr)
|
|||
|
|
{
|
|||
|
|
u32 enable_status = FI2cGetEnable(addr);
|
|||
|
|
u32 ret = FI2C_SUCCESS;
|
|||
|
|
u32 reg_val = 0;
|
|||
|
|
|
|||
|
|
if (FI2C_IC_ENABLE == enable_status)
|
|||
|
|
ret = FI2cSetEnable(addr, FALSE);
|
|||
|
|
|
|||
|
|
if (FI2C_SUCCESS == ret)
|
|||
|
|
FI2C_WRITE_REG32(addr, FI2C_SAR_OFFSET, (sar_addr & FI2C_IC_SAR_MASK));
|
|||
|
|
|
|||
|
|
if (FI2C_IC_ENABLE == enable_status)
|
|||
|
|
ret = FI2cSetEnable(addr, TRUE);
|
|||
|
|
|
|||
|
|
return ret;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FI2cFlushRxFifo
|
|||
|
|
* @msg: 等待接收Fifo传输完成
|
|||
|
|
* @return {*}
|
|||
|
|
* @param {uintptr} addr, I2C控制器基地址
|
|||
|
|
*/
|
|||
|
|
FError FI2cFlushRxFifo(uintptr addr)
|
|||
|
|
{
|
|||
|
|
u8 data;
|
|||
|
|
int timeout = 0;
|
|||
|
|
FError ret = FI2C_SUCCESS;
|
|||
|
|
|
|||
|
|
/* read data to trigger trans until fifo empty */
|
|||
|
|
while (FI2C_GET_STATUS(addr) & FI2C_STATUS_RFNE)
|
|||
|
|
{
|
|||
|
|
data = FI2C_READ_DATA(addr);
|
|||
|
|
|
|||
|
|
if (FI2C_TIMEOUT < ++timeout)
|
|||
|
|
{
|
|||
|
|
ret = FI2C_TIMEOUT;
|
|||
|
|
FI2C_ERROR("timeout when flush fifo");
|
|||
|
|
break;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return ret;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FI2cClearIntrBits
|
|||
|
|
* @msg: 清除中断状态位，返回清除前的中断状态
|
|||
|
|
* @return {*}
|
|||
|
|
* @param {uintptr} addr, I2C控制器基地址
|
|||
|
|
* @param {u32} *last_err_p, Abort错误
|
|||
|
|
*/
|
|||
|
|
u32 FI2cClearIntrBits(uintptr addr, u32 *last_err_p)
|
|||
|
|
{
|
|||
|
|
FASSERT(last_err_p);
|
|||
|
|
|
|||
|
|
const u32 stat = FI2C_READ_INTR_STAT(addr);
|
|||
|
|
|
|||
|
|
/* read to clr intrrupt status bits */
|
|||
|
|
if (stat & FI2C_INTR_TX_ABRT)
|
|||
|
|
{
|
|||
|
|
*last_err_p = FI2C_READ_REG32(addr, FI2C_TX_ABRT_SOURCE_OFFSET); /* read out abort sources */
|
|||
|
|
FI2C_READ_REG32(addr, FI2C_CLR_TX_ABRT_OFFSET);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_RX_UNDER)
|
|||
|
|
FI2C_READ_REG32(addr, FI2C_CLR_RX_UNDER_OFFSET);
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_RX_OVER)
|
|||
|
|
FI2C_READ_REG32(addr, FI2C_CLR_RX_OVER_OFFSET);
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_TX_OVER)
|
|||
|
|
FI2C_READ_REG32(addr, FI2C_CLR_TX_OVER_OFFSET);
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_RX_DONE)
|
|||
|
|
FI2C_READ_REG32(addr, FI2C_CLR_RX_DONE_OFFSET);
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_ACTIVITY)
|
|||
|
|
FI2C_READ_REG32(addr, FI2C_CLR_ACTIVITY_OFFSET);
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_STOP_DET)
|
|||
|
|
FI2C_READ_REG32(addr, FI2C_CLR_STOP_DET_OFFSET);
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_START_DET)
|
|||
|
|
FI2C_READ_REG32(addr, FI2C_CLR_START_DET_OFFSET);
|
|||
|
|
|
|||
|
|
if (stat & FI2C_INTR_GEN_CALL)
|
|||
|
|
FI2C_READ_REG32(addr, FI2C_CLR_GEN_CALL_OFFSET);
|
|||
|
|
|
|||
|
|
return stat;
|
|||
|
|
}
|