403 lines
16 KiB
C
403 lines
16 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fxmac_intr.c
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* Date: 2022-04-06 14:46:52
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* LastEditTime: 2022-04-06 14:46:58
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* Description: This file is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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#include "fxmac.h"
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#include "fxmac_hw.h"
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#include "fassert.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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/**
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* @name: FXmacSetHandler
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* @msg: Install an asynchronous handler function for the given handler_type:
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*
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* @param instance_p is a pointer to the instance to be worked on.
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* @param handler_type indicates what interrupt handler type is.
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* FXMAC_HANDLER_DMASEND, FXMAC_HANDLER_DMARECV and
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* FXMAC_HANDLER_ERROR.
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* @param func_pointer is the pointer to the callback function
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* @param call_back_ref is the upper layer callback reference passed back when
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* when the callback function is invoked.
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*
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* @return {FError} FT_SUCCESS set is ok
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*/
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FError FXmacSetHandler(FXmac *instance_p, u32 handler_type,
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void *func_pointer, void *call_back_ref)
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{
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FError status;
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FASSERT(instance_p != NULL);
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FASSERT(func_pointer != NULL);
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FASSERT(instance_p->is_ready == (u32)FT_COMPONENT_IS_READY);
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status = (FError)(FT_SUCCESS);
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switch (handler_type)
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{
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case FXMAC_HANDLER_DMASEND:
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instance_p->send_irq_handler = ((FXmacIrqHandler)(void *)func_pointer);
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instance_p->send_args = call_back_ref;
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break;
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case FXMAC_HANDLER_DMARECV:
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instance_p->recv_irq_handler = ((FXmacIrqHandler)(void *)func_pointer);
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instance_p->recv_args = call_back_ref;
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break;
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case FXMAC_HANDLER_ERROR:
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instance_p->error_irq_handler = ((FXmacErrorIrqHandler)(void *)func_pointer);
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instance_p->error_args = call_back_ref;
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break;
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case FXMAC_HANDLER_LINKCHANGE:
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instance_p->link_change_handler = ((FXmacIrqHandler)(void *)func_pointer);
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instance_p->link_change_args = call_back_ref;
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break;
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case FXMAC_HANDLER_RESTART:
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instance_p->restart_handler = ((FXmacIrqHandler)(void *)func_pointer);
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instance_p->restart_args = call_back_ref;
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break;
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default:
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status = (FError)(FXMAC_ERR_INVALID_PARAM);
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break;
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}
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return status;
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}
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/**
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* @name: FXmacIntrHandler
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* @msg: 中断处理函数
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* @param {s32} vector is interrrupt num
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* @param {void} *args is a arguments variables
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* @return {*}
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* @note 目前中断只支持单queue的情况
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*/
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void FXmacIntrHandler(s32 vector, void *args)
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{
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u32 reg_isr;
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u32 reg_qx_isr;
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u32 reg_temp;
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u32 reg_ctrl;
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u32 tx_queue_id; /* 0 ~ FT_XMAC_QUEUE_MAX_NUM ,Index queue number */
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u32 rx_queue_id; /* 0 ~ FT_XMAC_QUEUE_MAX_NUM ,Index queue number */
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FXmac *instance_p = (FXmac *)args;
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FASSERT(instance_p != NULL);
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FASSERT(instance_p->is_ready == (u32)FT_COMPONENT_IS_READY);
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tx_queue_id = instance_p->tx_bd_queue.queue_id;
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rx_queue_id = instance_p->rx_bd_queue.queue_id;
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FASSERT((rx_queue_id < FT_XMAC_QUEUE_MAX_NUM) && (tx_queue_id < FT_XMAC_QUEUE_MAX_NUM))
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/* This ISR will try to handle as many interrupts as it can in a single
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* call. However, in most of the places where the user's error handler
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* is called, this ISR exits because it is expected that the user will
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* reset the device in nearly all instances.
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*/
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if ((u32)vector == instance_p->config.queue_irq_num[tx_queue_id])
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{
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if (tx_queue_id == 0)
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{
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reg_isr = FXMAC_READREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET);
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if ((reg_isr & FXMAC_IXR_TXCOMPL_MASK) != 0x00000000U)
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{
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/* Clear TX status register TX complete indication but preserve
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* error bits if there is any */
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FXMAC_WRITEREG32(instance_p->config.base_address,
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FXMAC_TXSR_OFFSET,
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((u32)FXMAC_TXSR_TXCOMPL_MASK |
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(u32)FXMAC_TXSR_USEDREAD_MASK));
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if (instance_p->send_irq_handler)
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{
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/* code */
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instance_p->send_irq_handler(instance_p->send_args);
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}
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/* add */
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FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TXCOMPL_MASK);
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}
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/* Transmit error conditions interrupt */
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if (((reg_isr & FXMAC_IXR_TX_ERR_MASK) != 0x00000000U) &&
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(!(reg_isr & FXMAC_IXR_TXCOMPL_MASK) != 0x00000000U))
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{
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/* Clear TX status register */
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reg_temp = FXMAC_READREG32(instance_p->config.base_address, FXMAC_TXSR_OFFSET);
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FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_TXSR_OFFSET, reg_temp);
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if (instance_p->error_irq_handler)
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{
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instance_p->error_irq_handler(instance_p->error_args, FXMAC_SEND, reg_temp);
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}
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/* add */
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FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TX_ERR_MASK);
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}
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/* add restart */
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if ((reg_isr & FXMAC_IXR_TXUSED_MASK) != 0x00000000U)
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{
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/* add */
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FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TXUSED_MASK);
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if (instance_p->restart_handler)
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{
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instance_p->restart_handler(instance_p->restart_args);
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}
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}
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/* link chaged */
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if ((reg_isr & FXMAC_IXR_LINKCHANGE_MASK) != 0x00000000U)
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{
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if (instance_p->link_change_handler)
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{
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instance_p->link_change_handler(instance_p->link_change_args);
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}
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FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_LINKCHANGE_MASK);
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}
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}
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else /* use queue number more than 0 */
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{
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reg_isr = FXMAC_READREG32(instance_p->config.base_address,
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FXMAC_QUEUE_REGISTER_OFFSET(FXMAC_INTQ1_STS_OFFSET, tx_queue_id));
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/* Transmit Q1 complete interrupt */
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if (((reg_isr & FXMAC_INTQUESR_TXCOMPL_MASK) != 0x00000000U))
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{
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/* Clear TX status register TX complete indication but preserve
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* error bits if there is any */
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FXMAC_WRITEREG32(instance_p->config.base_address,
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FXMAC_QUEUE_REGISTER_OFFSET(FXMAC_INTQ1_STS_OFFSET, tx_queue_id),
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FXMAC_INTQUESR_TXCOMPL_MASK);
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FXMAC_WRITEREG32(instance_p->config.base_address,
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FXMAC_TXSR_OFFSET,
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((u32)FXMAC_TXSR_TXCOMPL_MASK |
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(u32)FXMAC_TXSR_USEDREAD_MASK));
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instance_p->send_irq_handler(instance_p->send_args);
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}
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/* Transmit Q1 error conditions interrupt */
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if (((reg_isr & FXMAC_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
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((reg_isr & FXMAC_INTQ1SR_TXCOMPL_MASK) != 0x00000000U))
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{
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/* Clear Interrupt Q1 status register */
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FXMAC_WRITEREG32(instance_p->config.base_address,
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FXMAC_QUEUE_REGISTER_OFFSET(FXMAC_INTQ1_STS_OFFSET, tx_queue_id), reg_isr);
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instance_p->error_irq_handler(instance_p->error_args, FXMAC_SEND,
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reg_isr);
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}
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}
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}
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if ((u32)vector == instance_p->config.queue_irq_num[rx_queue_id])
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{
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if (rx_queue_id == 0)
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{
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reg_isr = FXMAC_READREG32(instance_p->config.base_address,
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FXMAC_ISR_OFFSET);
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/* Receive complete interrupt */
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if ((reg_isr & FXMAC_IXR_RXCOMPL_MASK) != 0x00000000U)
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{
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/* Clear RX status register RX complete indication but preserve
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* error bits if there is any */
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FXMAC_WRITEREG32(instance_p->config.base_address,
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FXMAC_RXSR_OFFSET,
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((u32)FXMAC_RXSR_FRAMERX_MASK |
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(u32)FXMAC_RXSR_BUFFNA_MASK));
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instance_p->recv_irq_handler(instance_p->recv_args);
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/* add */
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FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_RXCOMPL_MASK);
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}
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/* Receive error conditions interrupt */
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if ((reg_isr & FXMAC_IXR_RX_ERR_MASK) != 0x00000000U)
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{
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/* Clear RX status register */
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reg_temp = FXMAC_READREG32(instance_p->config.base_address,
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FXMAC_RXSR_OFFSET);
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FXMAC_WRITEREG32(instance_p->config.base_address,
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FXMAC_RXSR_OFFSET, reg_temp);
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/* Fix for CR # 692702. Write to bit 18 of net_ctrl
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* register to flush a packet out of Rx SRAM upon
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* an error for receive buffer not available. */
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if ((reg_isr & FXMAC_IXR_RXUSED_MASK) != 0x00000000U)
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{
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reg_ctrl = FXMAC_READREG32(instance_p->config.base_address,
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FXMAC_NWCTRL_OFFSET);
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reg_ctrl |= (u32)FXMAC_NWCTRL_FLUSH_DPRAM_MASK;
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/* add */
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reg_ctrl &= (u32)(~FXMAC_NWCTRL_RXEN_MASK);
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FXMAC_WRITEREG32(instance_p->config.base_address,
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FXMAC_NWCTRL_OFFSET, reg_ctrl);
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/* add */
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reg_ctrl |= (u32)FXMAC_NWCTRL_RXEN_MASK;
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FXMAC_WRITEREG32(instance_p->config.base_address,
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FXMAC_NWCTRL_OFFSET, reg_ctrl);
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}
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/* add */
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if ((reg_isr & FXMAC_IXR_RXOVR_MASK) != 0x00000000U)
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{
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FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_RXOVR_MASK);
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}
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/* add */
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if ((reg_isr & FXMAC_IXR_HRESPNOK_MASK) != 0x00000000U)
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{
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FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_HRESPNOK_MASK);
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}
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if (reg_temp != 0)
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{
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instance_p->error_irq_handler(instance_p->error_args,
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FXMAC_RECV, reg_temp);
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}
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}
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}
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else /* use queue number more than 0 */
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{
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reg_isr = FXMAC_READREG32(instance_p->config.base_address,
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FXMAC_QUEUE_REGISTER_OFFSET(FXMAC_INTQ1_STS_OFFSET, rx_queue_id));
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/* Receive complete interrupt */
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if ((reg_isr & FXMAC_INTQUESR_RCOMP_MASK) != 0x00000000U)
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{
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/* Clear RX status register RX complete indication but preserve
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* error bits if there is any */
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FXMAC_WRITEREG32(instance_p->config.base_address,
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FXMAC_QUEUE_REGISTER_OFFSET(FXMAC_INTQ1_STS_OFFSET, rx_queue_id),
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FXMAC_INTQUESR_RCOMP_MASK);
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instance_p->recv_irq_handler(instance_p->recv_args);
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}
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/* Receive error conditions interrupt */
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if ((reg_isr & FXMAC_IXR_RX_ERR_MASK) != 0x00000000U)
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{
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reg_ctrl =
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FXMAC_READREG32(instance_p->config.base_address,
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FXMAC_NWCTRL_OFFSET);
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reg_ctrl &= ~(u32)FXMAC_NWCTRL_RXEN_MASK;
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FXMAC_WRITEREG32(instance_p->config.base_address,
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FXMAC_NWCTRL_OFFSET, reg_ctrl);
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/* Clear RX status register */
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reg_temp = FXMAC_READREG32(instance_p->config.base_address,
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FXMAC_RXSR_OFFSET);
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FXMAC_WRITEREG32(instance_p->config.base_address,
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FXMAC_RXSR_OFFSET, reg_temp);
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/* Fix for CR # 692702. Write to bit 18 of net_ctrl
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* register to flush a packet out of Rx SRAM upon
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* an error for receive buffer not available. */
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|||
|
|
if ((reg_isr & FXMAC_IXR_RXUSED_MASK) != 0x00000000U)
|
|||
|
|
{
|
|||
|
|
reg_ctrl =
|
|||
|
|
FXMAC_READREG32(instance_p->config.base_address,
|
|||
|
|
FXMAC_NWCTRL_OFFSET);
|
|||
|
|
reg_ctrl |= (u32)FXMAC_NWCTRL_FLUSH_DPRAM_MASK;
|
|||
|
|
|
|||
|
|
FXMAC_WRITEREG32(instance_p->config.base_address,
|
|||
|
|
FXMAC_NWCTRL_OFFSET, reg_ctrl);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Clear RX status register RX complete indication but preserve
|
|||
|
|
* error bits if there is any */
|
|||
|
|
FXMAC_WRITEREG32(instance_p->config.base_address,
|
|||
|
|
FXMAC_QUEUE_REGISTER_OFFSET(FXMAC_INTQ1_STS_OFFSET, rx_queue_id),
|
|||
|
|
FXMAC_INTQUESR_RXUBR_MASK);
|
|||
|
|
instance_p->recv_irq_handler(instance_p->recv_args);
|
|||
|
|
|
|||
|
|
if (reg_temp != 0)
|
|||
|
|
{
|
|||
|
|
instance_p->error_irq_handler(instance_p->error_args,
|
|||
|
|
FXMAC_RECV, reg_temp);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FXmacQueueIrqDisable
|
|||
|
|
* @msg: Disable queue irq
|
|||
|
|
* @param {FXmac} *instance_p a pointer to the instance to be worked on.
|
|||
|
|
* @param {u32} queue_num queue number
|
|||
|
|
* @param {u32} mask is interrupt disable value mask
|
|||
|
|
*/
|
|||
|
|
void FXmacQueueIrqDisable(FXmac *instance_p, u32 queue_num, u32 mask)
|
|||
|
|
{
|
|||
|
|
FXmacConfig *config_p;
|
|||
|
|
FASSERT(instance_p != NULL);
|
|||
|
|
FASSERT(instance_p->is_ready == (u32)FT_COMPONENT_IS_READY);
|
|||
|
|
FASSERT(instance_p->config.max_queue_num > queue_num);
|
|||
|
|
config_p = &instance_p->config;
|
|||
|
|
|
|||
|
|
if (queue_num == 0)
|
|||
|
|
{
|
|||
|
|
FXMAC_WRITEREG32(config_p->base_address, FXMAC_IDR_OFFSET, mask & FXMAC_IXR_ALL_MASK);
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
FXMAC_WRITEREG32(config_p->base_address, FXMAC_INTQX_IDR_SIZE_OFFSET(queue_num), mask & FXMAC_IXR_ALL_MASK);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FXmacQueueIrqEnable
|
|||
|
|
* @msg: Enable queue irq
|
|||
|
|
* @param {FXmac} *instance_p a pointer to the instance to be worked on.
|
|||
|
|
* @param {u32} queue_num is queue number
|
|||
|
|
* @param {u32} mask is interrupt Enable value mask
|
|||
|
|
*/
|
|||
|
|
void FXmacQueueIrqEnable(FXmac *instance_p, u32 queue_num, u32 mask)
|
|||
|
|
{
|
|||
|
|
FXmacConfig *config_p;
|
|||
|
|
FASSERT(instance_p != NULL);
|
|||
|
|
FASSERT(instance_p->is_ready == (u32)FT_COMPONENT_IS_READY);
|
|||
|
|
FASSERT(instance_p->config.max_queue_num > queue_num);
|
|||
|
|
config_p = &instance_p->config;
|
|||
|
|
|
|||
|
|
if (queue_num == 0)
|
|||
|
|
{
|
|||
|
|
FXMAC_WRITEREG32(config_p->base_address, FXMAC_IER_OFFSET, mask & FXMAC_IXR_ALL_MASK);
|
|||
|
|
}
|
|||
|
|
else
|
|||
|
|
{
|
|||
|
|
FXMAC_WRITEREG32(config_p->base_address, FXMAC_INTQX_IER_SIZE_OFFSET(queue_num), mask & FXMAC_IXR_ALL_MASK);
|
|||
|
|
}
|
|||
|
|
}
|