536 lines
17 KiB
C
536 lines
17 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fadc.c
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 08:28:45
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* Description: This files is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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#include <string.h>
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#include "fgeneric_timer.h"
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#include "fkernel.h"
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#include "ftypes.h"
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#include "ferror_code.h"
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#include "fdebug.h"
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#include "fadc.h"
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#include "fadc_hw.h"
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#include "fparameters.h"
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#include "fassert.h"
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#include "fsleep.h"
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#define FADC_DEBUG_TAG "FT_ADC"
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#define FADC_DEBUG(format, ...) FT_DEBUG_PRINT_D(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FADC_INFO(format, ...) FT_DEBUG_PRINT_I(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FADC_WARN(format, ...) FT_DEBUG_PRINT_W(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FADC_ERROR(format, ...) FT_DEBUG_PRINT_E(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FADC_MAX_CLOCK_PRESC 16
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#define FADC_MAX_THRESHOLD 0x400
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/**
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* @name: FAdcPowerDownControl
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* @msg: Set power down signal
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* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
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* the configuration information for the specified adc module.
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* @param {u8} power_state, this parameter must be enable or disable.
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* @return err code information, FADC_SUCCESS indicates success，others indicates failed
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*/
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static FError FAdcPowerDownControl(FAdcCtrl *pctrl, u8 power_state)
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{
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FASSERT(pctrl != NULL);
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FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
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u32 reg_val = 0;
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uintptr base_addr = pctrl->config.base_addr;
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reg_val = FADC_READ_REG32(base_addr, FADC_CTRL_REG_OFFSET);
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if (power_state == FADC_CTRL_PD_ENABLE)
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{
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reg_val |= FADC_CTRL_REG_PD_EN;
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}
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else
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{
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reg_val &= ~(FADC_CTRL_REG_PD_EN);
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}
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FADC_WRITE_REG32(base_addr, FADC_CTRL_REG_OFFSET, reg_val);
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return FADC_SUCCESS;
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}
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/**
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* @name: FAdcChannelEnable
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* @msg: enable channel, corresponding to fix channel mode or multi channel mode.
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* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
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* the configuration information for the specified adc module.
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* @param {FAdcChannel} channel, adc channel number.
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* @param {boolean} state, TRUE-enable, FALSE-disable
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* @return void
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*/
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void FAdcChannelEnable(FAdcCtrl *pctrl, FAdcChannel channel, boolean state)
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{
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FASSERT(pctrl != NULL);
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FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
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FASSERT(channel < FADC_CHANNEL_NUM);
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u32 reg_val = 0;
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uintptr base_addr = pctrl->config.base_addr;
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reg_val = FADC_READ_REG32(base_addr, FADC_CTRL_REG_OFFSET);
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if (state == TRUE)
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{
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if (reg_val & FADC_CTRL_REG_FIX_CHANNEL)
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{
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reg_val &= ~(FADC_CTRL_REG_FIX_CHANNEL_NUM_MASK);
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reg_val |= FADC_CTRL_REG_FIX_CHANNEL_NUM(channel);
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}
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else
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{
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reg_val |= FADC_CTRL_REG_CHANNEL_EN(channel);
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}
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}
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else
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{
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/* fix channel mode, disable means stop convert */
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if (reg_val & FADC_CTRL_REG_FIX_CHANNEL)
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{
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reg_val &= ~(FADC_CTRL_REG_SOC_EN);
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}
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else
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{
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reg_val &= ~(FADC_CTRL_REG_CHANNEL_EN(channel));
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}
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}
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FADC_WRITE_REG32(base_addr, FADC_CTRL_REG_OFFSET, reg_val);
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}
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/**
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* @name: FAdcChannelThresholdSet
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* @msg: Set adc channel high_threshold and low_threshold.
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* you need use this function after FAdcConvertSet. If you want to use this function to
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* add other channel enable when the adc conversion is started, you need to restart the
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* adc convert start signal(adc_soc_en) after use to make the operation valid.
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* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
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* the configuration information for the specified adc module.
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* @param {FAdcChannel} channel, adc channel number.
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* @param {FAdcThresholdConfig} *threshold_config, pointer to adc channel threshold value struct.
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* @return err code information, FADC_SUCCESS indicates success，others indicates failed
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*/
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FError FAdcChannelThresholdSet(FAdcCtrl *pctrl, FAdcChannel channel, FAdcThresholdConfig *threshold_config)
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{
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FASSERT(pctrl != NULL);
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FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
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FASSERT(channel < FADC_CHANNEL_NUM);
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u16 low_threshold = threshold_config->low_threshold;
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u16 high_threshold = threshold_config->high_threshold;
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FASSERT(high_threshold < FADC_MAX_THRESHOLD);
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FASSERT(low_threshold < high_threshold);
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uintptr base_addr = pctrl->config.base_addr;
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u32 threshold = (FADC_LEVEL_REG_HIGH_LEVEL(high_threshold)) |
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(FADC_LEVEL_REG_LOW_LEVEL(low_threshold));
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FADC_WRITE_REG32(base_addr, (FADC_LEVEL_REG_OFFSET(channel)), threshold);
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return FADC_SUCCESS;
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}
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/**
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* @name: FAdcConvertSet
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* @msg: config adc convert parameters.
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* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
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* the configuration information for the specified adc module.
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* @param {FAdcConvertConfig} *convert_config, include convert mode，channel mode，
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* clock divider and convert_interval.
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* @return err code information, FADC_SUCCESS indicates success，others indicates failed
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*/
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FError FAdcConvertSet(FAdcCtrl *pctrl, FAdcConvertConfig *convert_config)
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{
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FASSERT(pctrl != NULL);
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FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
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u32 reg_val = 0;
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uintptr base_addr = pctrl->config.base_addr;
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reg_val = FADC_READ_REG32(base_addr, FADC_CTRL_REG_OFFSET);
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/* clk_div config */
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u32 clk_div = convert_config->clk_div;
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FASSERT(clk_div < FADC_MAX_CLOCK_PRESC);
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if (clk_div % 2 == 1)
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{
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FADC_ERROR("clk_div is not even.");
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return FADC_ERR_INVAL_PARM;
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}
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reg_val &= (~FADC_CTRL_REG_CLK_DIV_MASK);
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reg_val |= FADC_CTRL_REG_CLK_DIV(clk_div);
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/* config convert mode */
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FAdcConvertMode convert_mode = convert_config->convert_mode;
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FASSERT(convert_mode < FADC_CONVERT_MODE_NUM);
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if (convert_mode == FADC_SINGLE_CONVERT)
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{
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reg_val |= FADC_CTRL_REG_SINGLE_CONVERT;
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}
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else
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{
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reg_val &= ~(FADC_CTRL_REG_SINGLE_CONVERT);
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}
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/* config channel mode */
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FAdcChannelMode channel_mode = convert_config->channel_mode;
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FASSERT(channel_mode < FADC_CHANNEL_MODE_NUM);
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if (channel_mode == FADC_FIXED_CHANNEL)
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{
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reg_val |= FADC_CTRL_REG_FIX_CHANNEL;
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}
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else
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{
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reg_val &= ~(FADC_CTRL_REG_FIX_CHANNEL);
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}
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FADC_WRITE_REG32(base_addr, FADC_CTRL_REG_OFFSET, reg_val);
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/* config time interval between two converts */
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FADC_WRITE_REG32(base_addr, FADC_INTER_REG_OFFSET, convert_config->convert_interval);
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return FADC_SUCCESS;
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}
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/**
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* @name: FAdcInterruptEnable
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* @msg: enable channel interrupt.
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* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
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* the configuration information for the specified adc module.
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* @param {FAdcChannel} channel, adc channel number.
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* @param {FAdcIntrEvtType} event_type, interrupt event type
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* @return err code information, FADC_SUCCESS indicates success，others indicates failed
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*/
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FError FAdcInterruptEnable(FAdcCtrl *pctrl, FAdcChannel channel, FAdcIntrEventType event_type)
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{
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FASSERT(pctrl != NULL);
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FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
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uintptr base_addr = pctrl->config.base_addr;
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u32 reg_val = 0;
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reg_val = FADC_READ_REG32(base_addr, FADC_INTRMASK_REG_OFFSET);
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switch (event_type)
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{
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case FADC_INTR_EVENT_COVFIN: /* enable channel convert complete irq */
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reg_val &= ~(FADC_INTRMASK_REG_COVFIN_MASK(channel));
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break;
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case FADC_INTR_EVENT_DLIMIT:
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reg_val &= ~(FADC_INTRMASK_REG_DLIMIT_MASK(channel));
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break;
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case FADC_INTR_EVENT_ULIMIT:
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reg_val &= ~(FADC_INTRMASK_REG_ULIMIT_MASK(channel));
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break;
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case FADC_INTR_EVENT_ERROR:
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reg_val &= ~(FADC_INTRMASK_REG_ERR_MASK);
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break;
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default:
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break;
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}
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FADC_WRITE_REG32(base_addr, FADC_INTRMASK_REG_OFFSET, reg_val);
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return FADC_SUCCESS;
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}
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/**
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* @name: FAdcInterruptDisable
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* @msg: disable channel interrupt.
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* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
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* the configuration information for the specified adc module.
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* @param {FAdcChannel} channel, adc channel number.
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* @param {FAdcIntrEvtType} event_type, interrupt event type
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* @return err code information, FADC_SUCCESS indicates success，others indicates failed
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*/
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FError FAdcInterruptDisable(FAdcCtrl *pctrl, FAdcChannel channel, FAdcIntrEventType event_type)
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{
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FASSERT(pctrl != NULL);
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FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
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FASSERT(channel < FADC_CHANNEL_NUM);
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uintptr base_addr = pctrl->config.base_addr;
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u32 reg_val = 0;
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reg_val = FADC_READ_REG32(base_addr, FADC_INTRMASK_REG_OFFSET);
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switch (event_type)
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{
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case FADC_INTR_EVENT_COVFIN: /* enable channel convert complete irq */
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reg_val |= (FADC_INTRMASK_REG_COVFIN_MASK(channel));
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break;
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case FADC_INTR_EVENT_DLIMIT:
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reg_val |= (FADC_INTRMASK_REG_DLIMIT_MASK(channel));
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break;
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case FADC_INTR_EVENT_ULIMIT:
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reg_val |= (FADC_INTRMASK_REG_ULIMIT_MASK(channel));
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break;
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case FADC_INTR_EVENT_ERROR:
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reg_val |= (FADC_INTRMASK_REG_ERR_MASK);
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break;
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default:
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break;
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}
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FADC_WRITE_REG32(base_addr, FADC_INTRMASK_REG_OFFSET, reg_val);
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return FADC_SUCCESS;
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}
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/**
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* @name: FAdcConvertStart
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* @msg: Start adc convert.
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* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
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* the configuration information for the specified adc module.
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* @return
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*/
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void FAdcConvertStart(FAdcCtrl *pctrl)
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{
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FASSERT(pctrl != NULL);
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FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
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u32 reg_val = 0;
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uintptr base_addr = pctrl->config.base_addr;
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reg_val = FADC_READ_REG32(base_addr, FADC_CTRL_REG_OFFSET);
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reg_val |= FADC_CTRL_REG_SOC_EN;
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FADC_WRITE_REG32(base_addr, FADC_CTRL_REG_OFFSET, reg_val);
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}
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/**
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* @name: FAdcConvertStop
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* @msg: Stop adc convert.
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* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
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* the configuration information for the specified adc module.
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* @return
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*/
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void FAdcConvertStop(FAdcCtrl *pctrl)
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{
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FASSERT(pctrl != NULL);
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FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
|
|||
|
|
u32 reg_val = 0;
|
|||
|
|
uintptr base_addr = pctrl->config.base_addr;
|
|||
|
|
reg_val = FADC_READ_REG32(base_addr, FADC_CTRL_REG_OFFSET);
|
|||
|
|
reg_val &= (~FADC_CTRL_REG_SOC_EN);
|
|||
|
|
FADC_WRITE_REG32(base_addr, FADC_CTRL_REG_OFFSET, reg_val);
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FAdcInit
|
|||
|
|
* @msg: init adc variable configuration.
|
|||
|
|
* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
|
|||
|
|
* the configuration information for the specified adc module.
|
|||
|
|
* @param {FAdcConvertConfig} *convert_config, pointer to adc convert configuration
|
|||
|
|
* @return err code information, FADC_SUCCESS indicates success，others indicates failed
|
|||
|
|
*/
|
|||
|
|
FError FAdcVariableConfig(FAdcCtrl *pctrl, FAdcConvertConfig *convert_config)
|
|||
|
|
{
|
|||
|
|
FASSERT(pctrl != NULL);
|
|||
|
|
FASSERT(convert_config != NULL);
|
|||
|
|
|
|||
|
|
FError ret = FADC_SUCCESS;
|
|||
|
|
|
|||
|
|
/* disable power down signal */
|
|||
|
|
ret = FAdcPowerDownControl(pctrl, FADC_CTRL_PD_DISABLE);
|
|||
|
|
if (ret != FADC_SUCCESS)
|
|||
|
|
{
|
|||
|
|
FADC_ERROR("FAdcPowerDownControl failed.");
|
|||
|
|
return FADC_ERR_CMD_FAILED;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* set time interval between two converts */
|
|||
|
|
ret = FAdcConvertSet(pctrl, convert_config);
|
|||
|
|
if (ret != FADC_SUCCESS)
|
|||
|
|
{
|
|||
|
|
FADC_ERROR("FAdcConvertSet failed.");
|
|||
|
|
return FADC_ERR_CMD_FAILED;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return ret;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FAdcSingleConvertEnable
|
|||
|
|
* @msg: Enable single convert signal, when convert mode is set to single conversion.
|
|||
|
|
* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
|
|||
|
|
* the configuration information for the specified adc module.
|
|||
|
|
* @return err code information, FADC_SUCCESS indicates success，others indicates failed
|
|||
|
|
*/
|
|||
|
|
static FError FAdcSingleConvertEnable(FAdcCtrl *pctrl)
|
|||
|
|
{
|
|||
|
|
FASSERT(pctrl != NULL);
|
|||
|
|
FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
|
|||
|
|
u32 reg_val = 0;
|
|||
|
|
uintptr base_addr = pctrl->config.base_addr;
|
|||
|
|
reg_val = FADC_READ_REG32(base_addr, FADC_CTRL_REG_OFFSET);
|
|||
|
|
reg_val |= FADC_CTRL_REG_SINGLE_CONVERT_EN;
|
|||
|
|
FADC_WRITE_REG32(base_addr, FADC_CTRL_REG_OFFSET, reg_val);
|
|||
|
|
|
|||
|
|
return FADC_SUCCESS;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FAdcReadConvertResult
|
|||
|
|
* @msg: read adc channel convert result value.
|
|||
|
|
* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
|
|||
|
|
* the configuration information for the specified adc module.
|
|||
|
|
* @param {FAdcChannel} channel, adc channel number.
|
|||
|
|
* @param {u16} *val, pointer to adc convert result value.
|
|||
|
|
* @return err code information, FADC_SUCCESS indicates success，others indicates failed.
|
|||
|
|
*/
|
|||
|
|
FError FAdcReadConvertResult(FAdcCtrl *pctrl, FAdcChannel channel, u16 *val)
|
|||
|
|
{
|
|||
|
|
FASSERT(pctrl != NULL);
|
|||
|
|
FASSERT(channel < FADC_CHANNEL_NUM);
|
|||
|
|
FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
|
|||
|
|
int timeout = FADC_READ_DELAY;
|
|||
|
|
uintptr base_addr = pctrl->config.base_addr;
|
|||
|
|
|
|||
|
|
u32 reg_val = FADC_READ_REG32(base_addr, FADC_CTRL_REG_OFFSET);
|
|||
|
|
/* single conversion */
|
|||
|
|
if (reg_val & FADC_CTRL_REG_SINGLE_CONVERT)
|
|||
|
|
{
|
|||
|
|
FAdcSingleConvertEnable(pctrl);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
do
|
|||
|
|
{
|
|||
|
|
fsleep_millisec(10);
|
|||
|
|
}
|
|||
|
|
while ((!pctrl->convert_complete[channel]) && (0 <= --timeout));
|
|||
|
|
|
|||
|
|
if (0 >= timeout)
|
|||
|
|
{
|
|||
|
|
FADC_ERROR("timeout when read adc data, convert is not completed.");
|
|||
|
|
*val = 0;
|
|||
|
|
return FADC_ERR_TIMEOUT;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
FADC_CONVERT_UNCOMPLETE(pctrl->convert_complete[channel]);
|
|||
|
|
*val = pctrl->value[channel];
|
|||
|
|
|
|||
|
|
return FADC_SUCCESS;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FAdcReadFinishCnt
|
|||
|
|
* @msg: read adc channel convert finish count.
|
|||
|
|
* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
|
|||
|
|
* the configuration information for the specified adc module.
|
|||
|
|
* @param {FAdcChannel} channel, adc channel number.
|
|||
|
|
* @param {u32} *count, pointer to adc convert finish count.
|
|||
|
|
* @return err code information, FADC_SUCCESS indicates success，others indicates failed.
|
|||
|
|
*/
|
|||
|
|
FError FAdcReadFinishCnt(FAdcCtrl *pctrl, FAdcChannel channel, u32 *count)
|
|||
|
|
{
|
|||
|
|
FASSERT(pctrl != NULL);
|
|||
|
|
FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
|
|||
|
|
|
|||
|
|
uintptr base_addr = pctrl->config.base_addr;
|
|||
|
|
*count = FADC_READ_REG32(base_addr, FADC_FINISH_CNT_REG_OFFSET(channel));
|
|||
|
|
return FADC_SUCCESS;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FAdcReadHisLimit
|
|||
|
|
* @msg: read adc channel history limit value, include upper limit and lower limit.
|
|||
|
|
* @param {FAdcCtrl} *pctrl, pointer to a FAdcCtrl structure that contains
|
|||
|
|
* the configuration information for the specified adc module.
|
|||
|
|
* @param {FAdcChannel} channel, adc channel number.
|
|||
|
|
* @param {u16} *u_his_limit, pointer to adc convert history upper limit value.
|
|||
|
|
* @param {u16} *d_his_limit, pointer to adc convert history lower limit value.
|
|||
|
|
* @return err code information, FADC_SUCCESS indicates success，others indicates failed.
|
|||
|
|
*/
|
|||
|
|
FError FAdcReadHisLimit(FAdcCtrl *pctrl, FAdcChannel channel, u16 *u_his_limit, u16 *d_his_limit)
|
|||
|
|
{
|
|||
|
|
FASSERT(pctrl != NULL);
|
|||
|
|
FASSERT(FT_COMPONENT_IS_READY == pctrl->is_ready);
|
|||
|
|
u32 reg_val = 0;
|
|||
|
|
uintptr base_addr = pctrl->config.base_addr;
|
|||
|
|
|
|||
|
|
reg_val = FADC_READ_REG32(base_addr, FADC_HIS_LIMIT_REG_OFFSET(channel));
|
|||
|
|
|
|||
|
|
*u_his_limit = (reg_val & FADC_HIS_LIMIT_REG_UMASK) >> 16;
|
|||
|
|
*d_his_limit = (reg_val & FADC_HIS_LIMIT_REG_DMASK) ;
|
|||
|
|
|
|||
|
|
return FADC_SUCCESS;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FAdcDeInitialize
|
|||
|
|
* @msg: DeInitialization function for the device instance
|
|||
|
|
* @param {FAdcCtrl} *pctrl, instance of FADC controller
|
|||
|
|
* @return {*}
|
|||
|
|
*/
|
|||
|
|
void FAdcDeInitialize(FAdcCtrl *pctrl)
|
|||
|
|
{
|
|||
|
|
FASSERT(pctrl);
|
|||
|
|
|
|||
|
|
pctrl->is_ready = 0;
|
|||
|
|
memset(pctrl, 0, sizeof(*pctrl));
|
|||
|
|
|
|||
|
|
return;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @name: FAdcCfgInitialize
|
|||
|
|
* @msg: Initializes a specific instance such that it is ready to be used.
|
|||
|
|
* @param {FAdcCtrl} *pctrl, instance of FADC controller
|
|||
|
|
* @param {FAdcConfig} *input_config_p, Default configuration parameters of FADC
|
|||
|
|
* @return err code information, FADC_SUCCESS indicates success，others indicates failed
|
|||
|
|
*/
|
|||
|
|
FError FAdcCfgInitialize(FAdcCtrl *pctrl, const FAdcConfig *input_config_p)
|
|||
|
|
{
|
|||
|
|
FASSERT(pctrl && input_config_p);
|
|||
|
|
|
|||
|
|
FError ret = FADC_SUCCESS;
|
|||
|
|
/*
|
|||
|
|
* If the device is started, disallow the initialize and return a Status
|
|||
|
|
* indicating it is started. This allows the user to de-initialize the device
|
|||
|
|
* and reinitialize, but prevents a user from inadvertently
|
|||
|
|
* initializing.
|
|||
|
|
*/
|
|||
|
|
if (FT_COMPONENT_IS_READY == pctrl->is_ready)
|
|||
|
|
{
|
|||
|
|
FADC_WARN("device is already initialized!!!");
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/*Set default values and configuration data */
|
|||
|
|
FAdcDeInitialize(pctrl);
|
|||
|
|
|
|||
|
|
pctrl->config = *input_config_p;
|
|||
|
|
|
|||
|
|
pctrl->is_ready = FT_COMPONENT_IS_READY;
|
|||
|
|
|
|||
|
|
return ret;
|
|||
|
|
}
|