470 lines
15 KiB
C
470 lines
15 KiB
C
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//###########################################################################
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//
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// FILE: F2837xD_Ipc_Driver_Util.c
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//
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// TITLE: F2837xD Inter-Processor Communication (IPC) API Driver Utility
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// Functions
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//
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// DESCRIPTION:
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// API functions for inter-processor communications between the
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// Local and Remote CPU system.
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// The driver functions in this file are available only as
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// sample functions for application development. Due to the generic
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// nature of these functions and the cycle overhead inherent to a
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// function call, the code is not intended to be used in cases where
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// maximum efficiency is required in a system.
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//
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// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2
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// cores use this code.
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// The active debug CPU will be referred to as Local CPU and the other
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// CPU will be referred to as Remote CPU.
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// When using this source code in CPU1, the term "local"
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// will mean CPU1 and the term "remote" CPU will be mean CPU2.
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// When using this source code in CPU2, the term "local"
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// will mean CPU2 and the term "remote" CPU will be mean CPU1.
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//
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// The abbreviations LtoR and RtoL within the function names mean
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// Local to Remote and Remote to Local respectively.
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//
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//###########################################################################
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// $TI Release: F2837xD Support Library v3.05.00.00 $
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// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
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// $Copyright:
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// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//*****************************************************************************
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//
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//! \addtogroup ipc_util_api
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//! @{
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//
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//*****************************************************************************
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#include "F2837xD_device.h"
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#include "F2837xD_GlobalPrototypes.h"
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#include "F2837xD_Gpio_defines.h"
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#include "F2837xD_Ipc_drivers.h"
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//*****************************************************************************
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//
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//! Local CPU Acknowledges Remote to Local IPC Flag.
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//!
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//! \param ulFlags specifies the IPC flag mask for flags being acknowledged.
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//!
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//! This function will allow the Local CPU system to acknowledge/clear the IPC
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//! flag set by the Remote CPU system. The \e ulFlags parameter can be any of
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//! the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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IPCRtoLFlagAcknowledge (uint32_t ulFlags)
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{
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IpcRegs.IPCACK.all |= ulFlags;
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}
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//*****************************************************************************
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//
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//! Determines whether the given Remote to Local IPC flags are busy or not.
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//!
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//! \param ulFlags specifies Remote to Local IPC Flag number masks to check the
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//! status of.
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//!
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//! Allows the caller to determine whether the designated IPC flags are
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//! pending. The \e ulFlags parameter can be any of the IPC flag
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//! values: \b IPC_FLAG0 - \b IPC_FLAG31.
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//!
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//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated
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//! IPC flags are free.
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//
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//*****************************************************************************
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Uint16
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IPCRtoLFlagBusy (uint32_t ulFlags)
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{
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Uint16 returnStatus;
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if ((IpcRegs.IPCSTS.all & ulFlags) == 0)
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{
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returnStatus = 0;
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}
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else
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{
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returnStatus = 1;
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}
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return returnStatus;
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}
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//*****************************************************************************
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//
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//! Determines whether the given IPC flags are busy or not.
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//!
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//! \param ulFlags specifies Local to Remote IPC Flag number masks to check the
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//! status of.
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//!
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//! Allows the caller to determine whether the designated IPC flags are
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//! available for further control to master system communication. If \b 0 is
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//! returned, then all designated tasks have completed and are available.
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//! The \e ulFlags parameter can be any of the IPC flag
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//! values: \b IPC_FLAG0 - \b IPC_FLAG31.
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//!
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//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated
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//! IPC flags are free.
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//
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//*****************************************************************************
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Uint16
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IPCLtoRFlagBusy (uint32_t ulFlags)
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{
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Uint16 returnStatus;
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if ((IpcRegs.IPCFLG.all & ulFlags) == 0)
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{
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returnStatus = 0;
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}
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else
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{
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returnStatus = 1;
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}
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return returnStatus;
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}
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//*****************************************************************************
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//
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//! Local CPU Sets Local to Remote IPC Flag
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//!
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//! \param ulFlags specifies the IPC flag mask for flags being set.
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//!
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//! This function will allow the Local CPU system to set the designated IPC
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//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any
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//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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IPCLtoRFlagSet (uint32_t ulFlags)
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{
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IpcRegs.IPCSET.all |= ulFlags;
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}
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//*****************************************************************************
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//
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//! Local CPU Clears Local to Remote IPC Flag
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//!
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//! \param ulFlags specifies the IPC flag mask for flags being set.
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//!
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//! This function will allow the Local CPU system to set the designated IPC
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//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any
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//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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IPCLtoRFlagClear (uint32_t ulFlags)
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{
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IpcRegs.IPCCLR.all |= ulFlags;
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}
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//*****************************************************************************
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//
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//! Local Return CPU02 BOOT status
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//!
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//! This function returns the value at IPCBOOTSTS register.
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//!
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//! \return Boot status.
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//
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//*****************************************************************************
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uint32_t
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IPCGetBootStatus (void)
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{
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return(IpcRegs.IPCBOOTSTS);
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}
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#if defined (CPU1)
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//*****************************************************************************
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//! Executes a CPU02 control system bootloader.
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//!
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//! \param ulBootMode specifies which CPU02 control system boot mode to execute.
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//!
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//! This function will allow the CPU01 master system to boot the CPU02 control
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//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI,
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//! SCI, I2C, or parallel I/O. Unlike other IPCLite driver functions, this
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//! function blocks and waits until the control system boot ROM is configured
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//! and ready to receive CPU01 to CPU02 IPC INT0 interrupts. It then blocks and
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//! waits until IPC INT0 and IPC FLAG31 are available in the CPU02 boot ROM
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//! prior to sending the command to execute the selected bootloader. The \e
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//! ulBootMode parameter accepts one of the following values: \b
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//! C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL, \b
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//! C1C2_BROM_BOOTMODE_BOOT_FROM_SCI, \b
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//! C1C2_BROM_BOOTMODE_BOOT_FROM_SPI, \b
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//! C1C2_BROM_BOOTMODE_BOOT_FROM_I2C, \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN,
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//! \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM, \b
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//! C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH.
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//!
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//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is
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//! invalid and command was not sent.
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//
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//*****************************************************************************
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uint16_t
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IPCBootCPU2(uint32_t ulBootMode)
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{
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uint32_t bootStatus;
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uint16_t pin;
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uint16_t returnStatus = STATUS_PASS;
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//
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// If CPU2 has already booted, return a fail to let the application
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// know that something is out of the ordinary.
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//
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bootStatus = IPCGetBootStatus() & 0x0000000F;
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if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK)
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{
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//
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// Check if MSB is set as well
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//
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bootStatus = ((uint32_t)(IPCGetBootStatus() & 0x80000000)) >> 31U;
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if(bootStatus != 0)
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{
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returnStatus = STATUS_FAIL;
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return returnStatus;
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}
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}
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//
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// Wait until CPU02 control system boot ROM is ready to receive
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// CPU01 to CPU02 INT1 interrupts.
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//
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do
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{
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bootStatus = IPCGetBootStatus() & C2_BOOTROM_BOOTSTS_SYSTEM_READY;
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} while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY));
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//
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// Loop until CPU02 control system IPC flags 1 and 32 are available
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//
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while ((IPCLtoRFlagBusy(IPC_FLAG0) == 1) ||
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(IPCLtoRFlagBusy(IPC_FLAG31) == 1))
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{
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}
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if (ulBootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE)
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{
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returnStatus = STATUS_FAIL;
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}
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else
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{
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//
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// Based on boot mode, enable pull-ups on peripheral pins and
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// give GPIO pin control to CPU02 control system.
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//
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switch (ulBootMode)
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{
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case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI:
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EALLOW;
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//
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//SCIA connected to CPU02
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//
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DevCfgRegs.CPUSEL5.bit.SCI_A = 1;
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//
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//Allows CPU02 bootrom to take control of clock
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//configuration registers
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//
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ClkCfgRegs.CLKSEM.all = 0xA5A50000;
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ClkCfgRegs.LOSPCP.all = 0x0002;
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EDIS;
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GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
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GPIO_SetupPinMux(29,GPIO_MUX_CPU2,1);
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GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_ASYNC);
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GPIO_SetupPinMux(28,GPIO_MUX_CPU2,1);
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break;
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case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI:
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EALLOW;
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//
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//SPI-A connected to CPU02
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//
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DevCfgRegs.CPUSEL6.bit.SPI_A = 1;
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//
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//Allows CPU02 bootrom to take control of clock configuration
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// registers
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//
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ClkCfgRegs.CLKSEM.all = 0xA5A50000;
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EDIS;
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GPIO_SetupPinOptions(16, GPIO_INPUT, GPIO_ASYNC);
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GPIO_SetupPinMux(16,GPIO_MUX_CPU2,1);
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GPIO_SetupPinOptions(17, GPIO_INPUT, GPIO_ASYNC);
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GPIO_SetupPinMux(17,GPIO_MUX_CPU2,1);
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GPIO_SetupPinOptions(18, GPIO_INPUT, GPIO_ASYNC);
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GPIO_SetupPinMux(18,GPIO_MUX_CPU2,1);
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GPIO_SetupPinOptions(19, GPIO_OUTPUT, GPIO_ASYNC);
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GPIO_SetupPinMux(19,GPIO_MUX_CPU2,0);
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break;
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case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C:
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EALLOW;
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//
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//I2CA connected to CPU02
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//
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DevCfgRegs.CPUSEL7.bit.I2C_A = 1;
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//
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//Allows CPU2 bootrom to take control of clock
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//configuration registers
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//
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ClkCfgRegs.CLKSEM.all = 0xA5A50000;
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ClkCfgRegs.LOSPCP.all = 0x0002;
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EDIS;
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GPIO_SetupPinOptions(32, GPIO_INPUT, GPIO_ASYNC);
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GPIO_SetupPinMux(32,GPIO_MUX_CPU2,1);
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GPIO_SetupPinOptions(33, GPIO_INPUT, GPIO_ASYNC);
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GPIO_SetupPinMux(33,GPIO_MUX_CPU2,1);
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break;
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case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL:
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for(pin=58;pin<=65;pin++)
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|
|
{
|
||
|
|
GPIO_SetupPinOptions(pin, GPIO_INPUT, GPIO_ASYNC);
|
||
|
|
GPIO_SetupPinMux(pin,GPIO_MUX_CPU2,0);
|
||
|
|
}
|
||
|
|
|
||
|
|
GPIO_SetupPinOptions(69, GPIO_OUTPUT, GPIO_ASYNC);
|
||
|
|
GPIO_SetupPinMux(69,GPIO_MUX_CPU2,0);
|
||
|
|
|
||
|
|
GPIO_SetupPinOptions(70, GPIO_INPUT, GPIO_ASYNC);
|
||
|
|
GPIO_SetupPinMux(70,GPIO_MUX_CPU2,0);
|
||
|
|
break;
|
||
|
|
|
||
|
|
|
||
|
|
case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN:
|
||
|
|
//
|
||
|
|
//Set up the GPIO mux to bring out CANATX on GPIO71
|
||
|
|
//and CANARX on GPIO70
|
||
|
|
//
|
||
|
|
EALLOW;
|
||
|
|
GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95
|
||
|
|
|
||
|
|
//
|
||
|
|
//Give CPU2 control just in case
|
||
|
|
//
|
||
|
|
GpioCtrlRegs.GPCCSEL1.bit.GPIO71 = GPIO_MUX_CPU2;
|
||
|
|
|
||
|
|
//
|
||
|
|
//Set the extended mux to 0x5
|
||
|
|
//
|
||
|
|
GpioCtrlRegs.GPCGMUX1.bit.GPIO71 = 0x1;
|
||
|
|
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 0x1;
|
||
|
|
|
||
|
|
//
|
||
|
|
//Set qualification to async just in case
|
||
|
|
//
|
||
|
|
GpioCtrlRegs.GPCQSEL1.bit.GPIO71 = 0x3;
|
||
|
|
|
||
|
|
GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95
|
||
|
|
|
||
|
|
//
|
||
|
|
//Give CPU2 control just in case
|
||
|
|
//
|
||
|
|
GpioCtrlRegs.GPCCSEL1.bit.GPIO70 = GPIO_MUX_CPU2;
|
||
|
|
|
||
|
|
//
|
||
|
|
//Set the extended mux to bring out CANATX
|
||
|
|
//
|
||
|
|
GpioCtrlRegs.GPCGMUX1.bit.GPIO70 = 0x1;
|
||
|
|
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 0x1;
|
||
|
|
|
||
|
|
//
|
||
|
|
//Set qualification to async just in case
|
||
|
|
//
|
||
|
|
GpioCtrlRegs.GPCQSEL1.bit.GPIO70 = 0x3;
|
||
|
|
GpioCtrlRegs.GPCLOCK.all = 0xFFFFFFFF; //Lock GPIOs 64-95
|
||
|
|
ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = 0x0;
|
||
|
|
CpuSysRegs.PCLKCR10.bit.CAN_A = 1;
|
||
|
|
EDIS;
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
//CPU01 to CPU02 IPC Boot Mode Register
|
||
|
|
//
|
||
|
|
IpcRegs.IPCBOOTMODE = ulBootMode;
|
||
|
|
|
||
|
|
//
|
||
|
|
// CPU01 To CPU02 IPC Command Register
|
||
|
|
//
|
||
|
|
IpcRegs.IPCSENDCOM = BROM_IPC_EXECUTE_BOOTMODE_CMD;
|
||
|
|
|
||
|
|
//
|
||
|
|
// CPU01 to CPU02 IPC flag register
|
||
|
|
//
|
||
|
|
IpcRegs.IPCSET.all = 0x80000001;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
return returnStatus;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|
||
|
|
//*****************************************************************************
|
||
|
|
// Close the Doxygen group.
|
||
|
|
//! @}
|
||
|
|
//*****************************************************************************
|
||
|
|
|
||
|
|
|