334 lines
10 KiB
C
334 lines
10 KiB
C
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/**
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******************************************************************************
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* @brief PWR functions of the firmware library.
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "gd32f10x_pwr.h"
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#include "gd32f10x_rcc.h"
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/** @addtogroup GD32F10x_Firmware
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* @{
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*/
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/** @defgroup PWR
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* @brief PWR driver modules
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* @{
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*/
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/** @defgroup PWR_Private_Defines
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* @{
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*/
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/* Left shift SBF or WUF(PWR_STR) to SBFR or WUFR(PWR_CTLR) */
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#define BIT_SHIFT 2
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/**
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* @}
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*/
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/** @defgroup PWR_Private_Functions
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* @{
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*/
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/**
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* @brief Reset the PWR peripheral registers.
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* @param None
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* @retval None
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*/
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void PWR_DeInit(void)
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{
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RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_PWRRST, ENABLE);
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RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_PWRRST, DISABLE);
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}
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/**
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* @brief Enable or disable write access to the registers in Backup domain.
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* @note After reset, any write access to the registers in Backup domain is disabled.
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* This bit has to be set to enable write access to these registers.
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* @param NewValue: New value of write access state to the registers in Backup domain.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_BackupAccess_Enable(TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable the Backup Domain Access */
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PWR->CTLR |= PWR_CTLR_BKPWE;
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} else {
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/* Disable the Backup Domain Access */
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PWR->CTLR &= ~((uint32_t)PWR_CTLR_BKPWE);
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}
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}
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/**
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* @brief Enable or disable the LVD(Low Voltage Detector), and configure the voltage
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* threshold detected by the LVD.
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* @note The LVDE bit controls whether LVD is enabled or not, while the LVDT[2:0]
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* bits select the LVDT from 2.2V to 2.9V.
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* @note The LVD is stopped in Standby mode.
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* @param PWR_LVDT: the LVD threshold.
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* This parameter can be one of the following values:
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* @arg PWR_LVDT_0
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* @arg PWR_LVDT_1
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* @arg PWR_LVDT_2
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* @arg PWR_LVDT_3
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* @arg PWR_LVDT_4
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* @arg PWR_LVDT_5
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* @arg PWR_LVDT_6
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* @arg PWR_LVDT_7
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* @param NewValue: New value of the LVD state.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_LVDConfig(uint32_t PWR_LVDT, TypeState NewValue)
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{
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uint32_t temp = 0;
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temp = PWR->CTLR;
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/* Clear LVDT[7:5] bits */
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temp &= ~((uint32_t)PWR_CTLR_LVDT);
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/* Set LVDT[7:5] bits according to PWR_LVDT value */
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temp |= PWR_LVDT;
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/* Store the new value */
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PWR->CTLR = temp;
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/* Enable or disable the LVD */
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if (NewValue != DISABLE) {
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/* Enable the LVD */
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PWR->CTLR |= PWR_CTLR_LVDE;
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} else {
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/* Disable the LVD */
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PWR->CTLR &= ~((uint32_t)PWR_CTLR_LVDE);
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}
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}
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/**
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* @brief Enable or disable the WakeUp Pin(PA0 pin) function.
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* @note If WUPE is set before entering the power saving mode,
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* a rising edge on the WKUP Pin wakes up the system from the power
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* saving mode. As the WKUP pin is active high, it will setup
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* an input pull down mode when this bit is high.
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* @param NewValue: New value of the WKUP Pin state.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void PWR_WKUP_Pin_Enable(TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable the WKUP pin */
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PWR->STR |= PWR_STR_WUPE;
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} else {
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/* Disable the WKUP pin */
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PWR->STR &= ~PWR_STR_WUPE;
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}
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}
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/**
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*@verbatim
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[..] The GD32F10x series of devices provide three types of power saving modes.
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*** Sleep mode ***
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==================
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[..] The Sleep mode is based on the SLEEPING mode of the Cortex-M3. In Sleep
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mode, only clock of Cortex-M3 is off.
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(+) Entry:
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(++) To enter the Sleep mode, it is only necessary to clear SLEEPDEEP bit
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in the Cortex-M3 System Control Register, and execute a WFI or WFE
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instruction.
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(++) The Sleep mode is entered using the PWR_SLEEPMode_Entry() function.
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(+) Wakeup:
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(++) Any interrupt for WFI or Any event for WFE.
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(+) Wakeup Latency:
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(++) None
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*** Deep-sleep mode ***
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=================
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[..] The Deep-sleep mode is based on the SLEEPDEEP mode of the Cortex-M3. In
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Deep-sleep mode, all clocks in the 1.2V domain are off, and all of HSI,
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HSE and PLL are disabled. The LDO can operate normally or in low
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power mode depending on the LDOLP bit in the PWR_CTLR register.
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(+) Entry:
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(++) Before entering the Deep-sleep mode, it is necessary to set the
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SLEEPDEEP bit in the Cortex-M3 System Control Register, and clear
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the SDBM bit in the PWR_CTLR register.
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(++) The Deep-sleep mode is entered using the PWR_DEEPSLEEPMode_Entry()
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function.
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(+) Wakeup:
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(++) Any interrupt or event from EXTI Lines.
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(+) Wakeup Latency:
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(++) HSI wakeup time; LDO wakeup time if LDO is in low power mode.
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*** Standby mode ***
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====================
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[..] The Standby mode is based on the SLEEPDEEP mode of the Cortex-M3. In Standby
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mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
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HSI, HSE and PLL are disabled. Besides, the contents of SRAM and
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registers(except Backup Registers) are lost in Standby mode.
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(+) Entry:
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(++) Before entering the Standby mode, it is necessary to set the
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SLEEPDEEP bit in the Cortex-M3 System Control Register, and set
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the SDBM bit in the PWR_CTLR register, and clear WUF bit in the
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PWR_STR register. .
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(++) The Standby mode is entered using the PWR_STDBYMode_Entry() function.
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(+) Wakeup:
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(++) NRST pin, WKUP pin rising edge, RTC alarm, IWDG reset.
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(+) Wakeup Latency:
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(++) Power on sequence
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*@endverbatim
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*/
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/**
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* @brief Enter Sleep mode.
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* @note By default, this function selects the Sleep-now entry mechanism (SLEEPONEXIT = 0).
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* @param PWR_SLEEPENTRY: WFI or WFE instruction.
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* This parameter can be one of the following values:
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* @arg PWR_SLEEPENTRY_WFI: enter Sleep mode with WFI instruction
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* @arg PWR_SLEEPENTRY_WFE: enter Sleep mode with WFE instruction
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* @retval None
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*/
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void PWR_SLEEPMode_Entry(uint8_t PWR_SLEEPENTRY)
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{
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/* Clear SLEEPDEEP bit of Cortex-M3 System Control Register */
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SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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/* Select WFI or WFE to enter Sleep mode */
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if (PWR_SLEEPENTRY == PWR_SLEEPENTRY_WFI) {
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__WFI();
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} else {
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__WFE();
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}
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}
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/**
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* @brief Enter Deep-sleep mode.
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* @note When exiting Deep-sleep mode, the HSI is selected as the system clock.
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* @note An additional wakeup delay will be incurred if the LDO operates in
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* low power mode.
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* @param PWR_LDO: the LDO state in Deep-sleep mode.
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* This parameter can be one of the following values:
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* @arg PWR_LDO_ON: Deep-sleep mode with LDO ON
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* @arg PWR_LDO_LOWPOWER: Deep-sleep mode with LDO in low power mode
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* @param PWR_DEEPSLEEPENTRY: WFI or WFE instruction.
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* This parameter can be one of the following values:
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* @arg PWR_DEEPSLEEPENTRY_WFI: enter Deep-sleep mode with WFI instruction
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* @arg PWR_DEEPSLEEPENTRY_WFE: enter Deep-sleep mode with WFE instruction
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* @retval None
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*/
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void PWR_DEEPSLEEPMode_Entry(uint32_t PWR_LDO, uint8_t PWR_DEEPSLEEPENTRY)
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{
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uint32_t temp = 0;
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/* Select the LDO state in Deep-sleep mode */
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temp = PWR->CTLR;
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/* Clear SDBM and LDOLP bits, and select Deep-sleep mode */
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temp &= ~((uint32_t)(PWR_CTLR_SDBM | PWR_CTLR_LDOLP));
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/* Set LDOLP bit according to PWR_LDO value, and select the LDO's state */
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temp |= PWR_LDO;
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/* Store the new value */
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PWR->CTLR = temp;
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/* Set SLEEPDEEP bit of Cortex-M3 System Control Register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* Select WFI or WFE to enter Deep-sleep mode */
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if (PWR_DEEPSLEEPENTRY == PWR_DEEPSLEEPENTRY_WFI) {
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__WFI();
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} else {
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__SEV();
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__WFE();
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__WFE();
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}
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/* Reset SLEEPDEEP bit of Cortex-M3 System Control Register */
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SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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}
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/**
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* @brief Enter Standby mode.
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* @note The Standby mode achieves the lowest power consumption, but spends
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* longest time to wake up.
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* @note When exiting from the Standby mode, a power-on reset occurs and the
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* Cortex-M3 will execute instructions code from the 0x0000_0000 address.
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* @param PWR_STDBYENTRY: WFI or WFE instruction.
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* This parameter can be one of the following values:
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* @arg PWR_STDBYENTRY_WFI: enter Standby mode with WFI instruction
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* @arg PWR_STDBYENTRY_WFE: enter Standby mode with WFE instruction
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* @retval None
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*/
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void PWR_STDBYMode_Entry(uint8_t PWR_STDBYENTRY)
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{
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/* Set SLEEPDEEP bit of Cortex-M3 System Control Register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* Set SDBM bit, and select Standby mode */
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PWR->CTLR |= PWR_CTLR_SDBM;
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/* Reset Wakeup flag */
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PWR->CTLR |= PWR_CTLR_WUFR;
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/* Select WFI or WFE to enter Standby mode */
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if (PWR_STDBYENTRY == PWR_STDBYENTRY_WFI) {
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__WFI();
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} else {
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__WFE();
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}
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}
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/**
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* @brief Get the bit flag of some PWR_STR registers.
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* @param PWR_FLAG: the flag of PWR_STR registers.
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* This parameter can be one of the following values:
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* @arg PWR_FLAG_WKUP: WakeUp flag. This flag indicates that a wakeup
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* event was received from the WKUP pin or from the RTC alarm,
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* IWDG reset or NRST pin.
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* @arg PWR_FLAG_STB: StandBy flag. This flag indicates that the
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* system has been in Standby mode.
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* @arg PWR_FLAG_LVDF: LVD State flag. This flag is valid only if LVD
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* is enabled by the PWR_LVD_Config()function.
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* @retval The new value of PWR_FLAG (SET or RESET).
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*/
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TypeState PWR_GetBitState(uint32_t PWR_FLAG)
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{
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/* Check and get the selected PWR flag */
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if ((PWR->STR & PWR_FLAG) != (uint32_t)RESET) {
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/* PWR_FLAG bit is SET */
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return SET;
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} else {
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/* PWR_FLAG bit is RESET */
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return RESET;
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}
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}
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/**
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* @brief Clear the bit flag of some PWR_STR registers.
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* @param PWR_FLAG: the flag of PWR_STR registers.
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* This parameter can be one of the following values:
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* @arg PWR_FLAG_WKUP: Wake_Up flag
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* @arg PWR_FLAG_STB: StandBy flag
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* @retval None
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*/
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void PWR_ClearBitState(uint32_t PWR_FLAG)
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{
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/* Clear the selected PWR flag */
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PWR->CTLR |= PWR_FLAG << BIT_SHIFT;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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