181 lines
4.5 KiB
ArmAsm
181 lines
4.5 KiB
ArmAsm
|
/*
|
||
|
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||
|
|
*
|
||
|
|
* SPDX-License-Identifier: Apache-2.0
|
||
|
|
*
|
||
|
|
* Change Logs:
|
||
|
|
* Date Author Notes
|
||
|
|
* 2018/10/28 Bernard The unify RISC-V porting implementation
|
||
|
|
*/
|
||
|
|
|
||
|
|
#include "cpuport.h"
|
||
|
|
|
||
|
|
/*
|
||
|
|
* rt_base_t rt_hw_interrupt_disable(void);
|
||
|
|
*/
|
||
|
|
.globl rt_hw_interrupt_disable
|
||
|
|
rt_hw_interrupt_disable:
|
||
|
|
csrrci a0, mstatus, 8
|
||
|
|
ret
|
||
|
|
|
||
|
|
/*
|
||
|
|
* void rt_hw_interrupt_enable(rt_base_t level);
|
||
|
|
*/
|
||
|
|
.globl rt_hw_interrupt_enable
|
||
|
|
rt_hw_interrupt_enable:
|
||
|
|
csrw mstatus, a0
|
||
|
|
ret
|
||
|
|
|
||
|
|
/*
|
||
|
|
* void rt_hw_context_switch_to(rt_ubase_t to)
|
||
|
|
* a0 --> to
|
||
|
|
*/
|
||
|
|
.globl rt_hw_context_switch_to
|
||
|
|
rt_hw_context_switch_to:
|
||
|
|
LOAD sp, (a0)
|
||
|
|
|
||
|
|
/* load epc from stack */
|
||
|
|
LOAD a0, 0 * REGBYTES(sp)
|
||
|
|
csrw mepc, a0
|
||
|
|
LOAD x1, 1 * REGBYTES(sp)
|
||
|
|
/* load mstatus from stack */
|
||
|
|
LOAD a0, 2 * REGBYTES(sp)
|
||
|
|
csrw mstatus, a0
|
||
|
|
LOAD x4, 4 * REGBYTES(sp)
|
||
|
|
LOAD x5, 5 * REGBYTES(sp)
|
||
|
|
LOAD x6, 6 * REGBYTES(sp)
|
||
|
|
LOAD x7, 7 * REGBYTES(sp)
|
||
|
|
LOAD x8, 8 * REGBYTES(sp)
|
||
|
|
LOAD x9, 9 * REGBYTES(sp)
|
||
|
|
LOAD x10, 10 * REGBYTES(sp)
|
||
|
|
LOAD x11, 11 * REGBYTES(sp)
|
||
|
|
LOAD x12, 12 * REGBYTES(sp)
|
||
|
|
LOAD x13, 13 * REGBYTES(sp)
|
||
|
|
LOAD x14, 14 * REGBYTES(sp)
|
||
|
|
LOAD x15, 15 * REGBYTES(sp)
|
||
|
|
LOAD x16, 16 * REGBYTES(sp)
|
||
|
|
LOAD x17, 17 * REGBYTES(sp)
|
||
|
|
LOAD x18, 18 * REGBYTES(sp)
|
||
|
|
LOAD x19, 19 * REGBYTES(sp)
|
||
|
|
LOAD x20, 20 * REGBYTES(sp)
|
||
|
|
LOAD x21, 21 * REGBYTES(sp)
|
||
|
|
LOAD x22, 22 * REGBYTES(sp)
|
||
|
|
LOAD x23, 23 * REGBYTES(sp)
|
||
|
|
LOAD x24, 24 * REGBYTES(sp)
|
||
|
|
LOAD x25, 25 * REGBYTES(sp)
|
||
|
|
LOAD x26, 26 * REGBYTES(sp)
|
||
|
|
LOAD x27, 27 * REGBYTES(sp)
|
||
|
|
LOAD x28, 28 * REGBYTES(sp)
|
||
|
|
LOAD x29, 29 * REGBYTES(sp)
|
||
|
|
LOAD x30, 30 * REGBYTES(sp)
|
||
|
|
LOAD x31, 31 * REGBYTES(sp)
|
||
|
|
|
||
|
|
addi sp, sp, 32 * REGBYTES
|
||
|
|
mret
|
||
|
|
|
||
|
|
/*
|
||
|
|
* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to)
|
||
|
|
* a0 --> from
|
||
|
|
* a1 --> to
|
||
|
|
*/
|
||
|
|
.globl rt_hw_context_switch
|
||
|
|
rt_hw_context_switch:
|
||
|
|
|
||
|
|
/* saved from thread context
|
||
|
|
* x1/ra -> sp(0)
|
||
|
|
* x1/ra -> sp(1)
|
||
|
|
* mstatus.mie -> sp(2)
|
||
|
|
* x(i) -> sp(i-4)
|
||
|
|
*/
|
||
|
|
addi sp, sp, -32 * REGBYTES
|
||
|
|
STORE sp, (a0)
|
||
|
|
|
||
|
|
STORE x1, 0 * REGBYTES(sp)
|
||
|
|
STORE x1, 1 * REGBYTES(sp)
|
||
|
|
|
||
|
|
csrr a0, mstatus
|
||
|
|
andi a0, a0, 8
|
||
|
|
beqz a0, save_mpie
|
||
|
|
li a0, 0x80
|
||
|
|
save_mpie:
|
||
|
|
STORE a0, 2 * REGBYTES(sp)
|
||
|
|
|
||
|
|
STORE x4, 4 * REGBYTES(sp)
|
||
|
|
STORE x5, 5 * REGBYTES(sp)
|
||
|
|
STORE x6, 6 * REGBYTES(sp)
|
||
|
|
STORE x7, 7 * REGBYTES(sp)
|
||
|
|
STORE x8, 8 * REGBYTES(sp)
|
||
|
|
STORE x9, 9 * REGBYTES(sp)
|
||
|
|
STORE x10, 10 * REGBYTES(sp)
|
||
|
|
STORE x11, 11 * REGBYTES(sp)
|
||
|
|
STORE x12, 12 * REGBYTES(sp)
|
||
|
|
STORE x13, 13 * REGBYTES(sp)
|
||
|
|
STORE x14, 14 * REGBYTES(sp)
|
||
|
|
STORE x15, 15 * REGBYTES(sp)
|
||
|
|
STORE x16, 16 * REGBYTES(sp)
|
||
|
|
STORE x17, 17 * REGBYTES(sp)
|
||
|
|
STORE x18, 18 * REGBYTES(sp)
|
||
|
|
STORE x19, 19 * REGBYTES(sp)
|
||
|
|
STORE x20, 20 * REGBYTES(sp)
|
||
|
|
STORE x21, 21 * REGBYTES(sp)
|
||
|
|
STORE x22, 22 * REGBYTES(sp)
|
||
|
|
STORE x23, 23 * REGBYTES(sp)
|
||
|
|
STORE x24, 24 * REGBYTES(sp)
|
||
|
|
STORE x25, 25 * REGBYTES(sp)
|
||
|
|
STORE x26, 26 * REGBYTES(sp)
|
||
|
|
STORE x27, 27 * REGBYTES(sp)
|
||
|
|
STORE x28, 28 * REGBYTES(sp)
|
||
|
|
STORE x29, 29 * REGBYTES(sp)
|
||
|
|
STORE x30, 30 * REGBYTES(sp)
|
||
|
|
STORE x31, 31 * REGBYTES(sp)
|
||
|
|
|
||
|
|
/* restore to thread context
|
||
|
|
* sp(0) -> epc;
|
||
|
|
* sp(1) -> ra;
|
||
|
|
* sp(i) -> x(i+2)
|
||
|
|
*/
|
||
|
|
LOAD sp, (a1)
|
||
|
|
|
||
|
|
/* resw ra to mepc */
|
||
|
|
LOAD a1, 0 * REGBYTES(sp)
|
||
|
|
csrw mepc, a1
|
||
|
|
LOAD x1, 1 * REGBYTES(sp)
|
||
|
|
|
||
|
|
/* force to machin mode(MPP=11) */
|
||
|
|
li a1, 0x00001800;
|
||
|
|
csrs mstatus, a1
|
||
|
|
LOAD a1, 2 * REGBYTES(sp)
|
||
|
|
csrs mstatus, a1
|
||
|
|
|
||
|
|
LOAD x4, 4 * REGBYTES(sp)
|
||
|
|
LOAD x5, 5 * REGBYTES(sp)
|
||
|
|
LOAD x6, 6 * REGBYTES(sp)
|
||
|
|
LOAD x7, 7 * REGBYTES(sp)
|
||
|
|
LOAD x8, 8 * REGBYTES(sp)
|
||
|
|
LOAD x9, 9 * REGBYTES(sp)
|
||
|
|
LOAD x10, 10 * REGBYTES(sp)
|
||
|
|
LOAD x11, 11 * REGBYTES(sp)
|
||
|
|
LOAD x12, 12 * REGBYTES(sp)
|
||
|
|
LOAD x13, 13 * REGBYTES(sp)
|
||
|
|
LOAD x14, 14 * REGBYTES(sp)
|
||
|
|
LOAD x15, 15 * REGBYTES(sp)
|
||
|
|
LOAD x16, 16 * REGBYTES(sp)
|
||
|
|
LOAD x17, 17 * REGBYTES(sp)
|
||
|
|
LOAD x18, 18 * REGBYTES(sp)
|
||
|
|
LOAD x19, 19 * REGBYTES(sp)
|
||
|
|
LOAD x20, 20 * REGBYTES(sp)
|
||
|
|
LOAD x21, 21 * REGBYTES(sp)
|
||
|
|
LOAD x22, 22 * REGBYTES(sp)
|
||
|
|
LOAD x23, 23 * REGBYTES(sp)
|
||
|
|
LOAD x24, 24 * REGBYTES(sp)
|
||
|
|
LOAD x25, 25 * REGBYTES(sp)
|
||
|
|
LOAD x26, 26 * REGBYTES(sp)
|
||
|
|
LOAD x27, 27 * REGBYTES(sp)
|
||
|
|
LOAD x28, 28 * REGBYTES(sp)
|
||
|
|
LOAD x29, 29 * REGBYTES(sp)
|
||
|
|
LOAD x30, 30 * REGBYTES(sp)
|
||
|
|
LOAD x31, 31 * REGBYTES(sp)
|
||
|
|
|
||
|
|
addi sp, sp, 32 * REGBYTES
|
||
|
|
mret
|