2022-07-30 14:10:51 +08:00
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-07-15 Emuzit first version
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*/
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#include <rthw.h>
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#include <rtdebug.h>
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#include <ipc/completion.h>
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#include <ipc/dataqueue.h>
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#ifdef RT_USING_SERIAL_V2
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#include <drivers/serial_v2.h>
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#else
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#include <drivers/serial.h>
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#endif
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2022-08-10 00:18:20 +08:00
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#include <drivers/pin.h>
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2022-07-30 14:10:51 +08:00
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#include "ch56x_sys.h"
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#include "ch56x_uart.h"
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#include "isr_sp.h"
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#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \
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!defined(BSP_USING_UART2) && !defined(BSP_USING_UART3)
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#error "Please define at least one UARTx"
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#endif
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2022-08-10 00:18:20 +08:00
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/* Type of irqn/rxd_pin/txd_pin are per uart driver perspective
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* to save some space, still compatible to RT api call, anyway.
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*/
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2022-07-30 14:10:51 +08:00
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struct serial_device
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{
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struct rt_serial_device parent;
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volatile struct uart_registers *reg_base;
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2022-08-10 00:18:20 +08:00
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uint8_t irqn;
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uint8_t resv;
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uint8_t rxd_pin;
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uint8_t txd_pin;
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2022-07-30 14:10:51 +08:00
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char *name;
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};
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#ifdef BSP_USING_UART0
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static struct serial_device serial_device_0 =
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{
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.reg_base = (struct uart_registers *)UART0_REG_BASE,
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.irqn = UART0_IRQn,
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2022-08-24 19:59:37 +08:00
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#ifndef BSP_USING_UART0_PIN_ALT
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2022-08-10 00:18:20 +08:00
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.rxd_pin = UART_RXD0_PIN,
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.txd_pin = UART_TXD0_PIN,
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2022-08-24 19:59:37 +08:00
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#else
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.rxd_pin = UART_RXD0_ALT,
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.txd_pin = UART_TXD0_ALT,
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#endif
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2022-07-30 14:10:51 +08:00
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.name = "uart0",
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};
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#endif
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#ifdef BSP_USING_UART1
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static struct serial_device serial_device_1 =
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{
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.reg_base = (struct uart_registers *)UART1_REG_BASE,
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.irqn = UART1_IRQn,
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2022-08-10 00:18:20 +08:00
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.rxd_pin = UART_RXD1_PIN,
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.txd_pin = UART_TXD1_PIN,
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2022-07-30 14:10:51 +08:00
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.name = "uart1",
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};
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#endif
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#ifdef BSP_USING_UART2
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static struct serial_device serial_device_2 =
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{
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.reg_base = (struct uart_registers *)UART2_REG_BASE,
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.irqn = UART2_IRQn,
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2022-08-10 00:18:20 +08:00
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.rxd_pin = UART_RXD2_PIN,
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.txd_pin = UART_TXD2_PIN,
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2022-07-30 14:10:51 +08:00
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.name = "uart2",
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};
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#endif
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#ifdef BSP_USING_UART3
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static struct serial_device serial_device_3 =
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{
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.reg_base = (struct uart_registers *)UART3_REG_BASE,
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.irqn = UART3_IRQn,
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2022-08-10 00:18:20 +08:00
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.rxd_pin = UART_RXD3_PIN,
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.txd_pin = UART_TXD3_PIN,
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2022-07-30 14:10:51 +08:00
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.name = "uart3",
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};
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#endif
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static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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struct serial_device *serial_device = (struct serial_device *)serial;
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volatile struct uart_registers *uxreg = serial_device->reg_base;
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union _uart_fcr fcr;
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union _uart_lcr lcr;
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uint32_t x;
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x = 10 * sys_hclk_get() / 8 / cfg->baud_rate;
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x = (x + 5) / 10;
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uxreg->DL = x;
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uxreg->DIV = 1;
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lcr.reg = 0;
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switch (cfg->data_bits)
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{
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case DATA_BITS_5:
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lcr.word_sz = LCR_DATA_BITS_5;
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break;
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case DATA_BITS_6:
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lcr.word_sz = LCR_DATA_BITS_6;
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break;
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case DATA_BITS_7:
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lcr.word_sz = LCR_DATA_BITS_7;
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break;
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case DATA_BITS_8:
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default:
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lcr.word_sz = LCR_DATA_BITS_8;
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break;
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}
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switch (cfg->stop_bits)
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{
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case STOP_BITS_2:
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lcr.stop_bit = LCR_STOP_BITS_2;
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break;
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case STOP_BITS_1:
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default:
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lcr.stop_bit = LCR_STOP_BITS_1;
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break;
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}
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switch (cfg->parity)
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{
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case PARITY_ODD:
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lcr.par_mod = LCR_PARITY_ODD;
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lcr.par_en = 1;
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break;
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case PARITY_EVEN:
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lcr.par_mod = LCR_PARITY_EVEN;
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lcr.par_en = 1;
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break;
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case PARITY_NONE:
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default:
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lcr.par_en = 0;
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break;
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}
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uxreg->LCR.reg = lcr.reg;
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fcr.reg = RB_FCR_FIFO_EN | RB_FCR_RX_FIFO_CLR | RB_FCR_TX_FIFO_CLR;
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fcr.fifo_trig = UART_1BYTE_TRIG;
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uxreg->FCR.reg = fcr.reg;
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/* TXD pin output enable */
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uxreg->IER.txd_en = 1;
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return RT_EOK;
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}
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static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *args)
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{
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struct serial_device *serial_device = (struct serial_device *)serial;
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volatile struct uart_registers *uxreg = serial_device->reg_base;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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uxreg->IER.recv_rdy = 0;
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uxreg->IER.line_stat = 0;
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uxreg->IER.thr_empty = 0;
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rt_hw_interrupt_mask(serial_device->irqn);
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break;
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case RT_DEVICE_CTRL_SET_INT:
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uxreg->FCR.fifo_trig = UART_1BYTE_TRIG;
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uxreg->MCR.int_oe = 1;
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uxreg->IER.recv_rdy = 1;
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uxreg->IER.line_stat = 1;
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if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
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{
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uxreg->IER.thr_empty = 1;
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}
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rt_hw_interrupt_umask(serial_device->irqn);
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break;
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default:
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break;
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}
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return RT_EOK;
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}
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static int uart_putc(struct rt_serial_device *serial, char ch)
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{
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struct serial_device *serial_device = (struct serial_device *)serial;
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volatile struct uart_registers *uxreg = serial_device->reg_base;
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if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
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{
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if (uxreg->TFC >= UART_FIFO_SIZE)
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return -1;
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}
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else
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{
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while (uxreg->TFC >= UART_FIFO_SIZE)
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{
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if (rt_thread_self() && rt_interrupt_get_nest() == 0)
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rt_thread_yield();
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}
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}
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uxreg->THR = ch;
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return 1;
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}
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static int uart_getc(struct rt_serial_device *serial)
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{
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struct serial_device *serial_device = (struct serial_device *)serial;
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volatile struct uart_registers *uxreg = serial_device->reg_base;
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/* UART_II_RECV_RDY is cleared by reading RBR */
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return (uxreg->RFC > 0) ? uxreg->RBR : -1;
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}
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static const struct rt_uart_ops uart_ops =
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{
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.configure = uart_configure,
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.control = uart_control,
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.putc = uart_putc,
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.getc = uart_getc,
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.dma_transmit = RT_NULL,
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};
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int rt_hw_uart_init(void)
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{
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struct serial_device *devices[4];
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/* Note: HCLK should be at least 8MHz for default 115200 baud to work */
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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int n = 0;
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#ifdef BSP_USING_UART3
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devices[n++] = &serial_device_3;
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#endif
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#ifdef BSP_USING_UART2
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devices[n++] = &serial_device_2;
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#endif
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#ifdef BSP_USING_UART1
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devices[n++] = &serial_device_1;
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#endif
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#ifdef BSP_USING_UART0
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devices[n++] = &serial_device_0;
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#endif
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while (--n >= 0)
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{
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2022-08-24 19:59:37 +08:00
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uint32_t flag;
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2022-07-30 14:10:51 +08:00
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struct serial_device *serial = devices[n];
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serial->parent.ops = &uart_ops;
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serial->parent.config = config;
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2022-08-24 19:59:37 +08:00
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rt_pin_mode(serial->txd_pin, PIN_MODE_OUTPUT);
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rt_pin_mode(serial->rxd_pin, PIN_MODE_INPUT_PULLUP);
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2022-08-10 00:18:20 +08:00
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2022-07-30 14:10:51 +08:00
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sys_clk_off_by_irqn(serial->irqn, SYS_SLP_CLK_ON);
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flag = RT_DEVICE_FLAG_RDWR |
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RT_DEVICE_FLAG_STREAM | // for converting '\n'
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RT_DEVICE_FLAG_INT_TX |
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RT_DEVICE_FLAG_INT_RX ;
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rt_hw_serial_register(&serial->parent, serial->name, flag, RT_NULL);
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/* rt_serial_open => uart_control with RT_DEVICE_CTRL_SET_INT */
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}
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return 0;
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}
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static void _uart_isr_common(struct serial_device *serial_device)
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{
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struct rt_serial_device *serial = &serial_device->parent;
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volatile struct uart_registers *uxreg = serial_device->reg_base;
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switch (uxreg->IIR.int_mask)
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{
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case UART_II_RECV_TOUT:
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/* FIXME: It's a bad idea to read RBR to clear UART_II_RECV_TOUT.
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* Race condition may happen that actual rx data is dropped.
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*/
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if (uxreg->RFC == 0)
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{
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uxreg->RBR;
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//rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_TIMEOUT);
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break;
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}
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/* pass through as if UART_II_RECV_RDY */
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case UART_II_RECV_RDY:
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
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break;
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case UART_II_THR_EMPTY:
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
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break;
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case UART_II_LINE_STAT:
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uxreg->LSR;
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break;
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case UART_II_MODEM_CHG:
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uxreg->MSR;
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break;
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case UART_II_SLV_ADDR:
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uxreg->IIR;
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break;
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default:
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break;
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}
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}
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#ifdef BSP_USING_UART0
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void uart0_irq_handler(void) __attribute__((interrupt()));
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void uart0_irq_handler(void)
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{
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isr_sp_enter();
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rt_interrupt_enter();
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_uart_isr_common(&serial_device_0);
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rt_interrupt_leave();
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isr_sp_leave();
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}
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#endif
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#ifdef BSP_USING_UART1
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void uart1_irq_handler(void) __attribute__((interrupt()));
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void uart1_irq_handler(void)
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{
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isr_sp_enter();
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rt_interrupt_enter();
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_uart_isr_common(&serial_device_1);
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rt_interrupt_leave();
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isr_sp_leave();
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}
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#endif
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#ifdef BSP_USING_UART2
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void uart2_irq_handler(void) __attribute__((interrupt()));
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void uart2_irq_handler(void)
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{
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isr_sp_enter();
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rt_interrupt_enter();
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_uart_isr_common(&serial_device_2);
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rt_interrupt_leave();
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isr_sp_leave();
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}
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#endif
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#ifdef BSP_USING_UART3
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void uart3_irq_handler(void) __attribute__((interrupt()));
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void uart3_irq_handler(void)
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{
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isr_sp_enter();
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rt_interrupt_enter();
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_uart_isr_common(&serial_device_3);
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rt_interrupt_leave();
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isr_sp_leave();
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}
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#endif
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