2021-05-21 17:03:30 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-05-20 bigmagic first version
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*/
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#ifndef PLIC_H
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#define PLIC_H
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#include <rtconfig.h>
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/*
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* This machine puts platform-level interrupt controller (PLIC) here.
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* Here only list PLIC registers in Machine mode.
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2021-05-21 18:39:41 +08:00
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*
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2021-05-21 17:03:30 +08:00
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*/
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#define VIRT_PLIC_BASE 0x0c000000L
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#define PLIC_PRIORITY_OFFSET (0x0)
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#define PLIC_PENDING_OFFSET (0x1000)
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#ifndef RISCV_S_MODE
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#define PLIC_MENABLE_OFFSET (0x2000)
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#define PLIC_MTHRESHOLD_OFFSET (0x200000)
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#define PLIC_MCLAIM_OFFSET (0x200004)
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#define PLIC_MCOMPLETE_OFFSET (0x200004)
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#define PLIC_ENABLE(hart) (VIRT_PLIC_BASE + PLIC_MENABLE_OFFSET + (hart) * 0x80)
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#define PLIC_THRESHOLD(hart) (VIRT_PLIC_BASE + PLIC_MTHRESHOLD_OFFSET + (hart) * 0x1000)
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#define PLIC_CLAIM(hart) (VIRT_PLIC_BASE + PLIC_MCLAIM_OFFSET + (hart) * 0x1000)
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#define PLIC_COMPLETE(hart) (VIRT_PLIC_BASE + PLIC_MCOMPLETE_OFFSET + (hart) * 0x1000)
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#else
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#define PLIC_SENABLE_OFFSET (0x2080)
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#define PLIC_STHRESHOLD_OFFSET (0x201000)
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#define PLIC_SCLAIM_OFFSET (0x201004)
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#define PLIC_SCOMPLETE_OFFSET (0x201004)
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#define PLIC_ENABLE(hart) (VIRT_PLIC_BASE + PLIC_SENABLE_OFFSET + (hart) * 0x80)
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#define PLIC_THRESHOLD(hart) (VIRT_PLIC_BASE + PLIC_STHRESHOLD_OFFSET + (hart) * 0x1000)
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#define PLIC_CLAIM(hart) (VIRT_PLIC_BASE + PLIC_SCLAIM_OFFSET + (hart) * 0x1000)
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#define PLIC_COMPLETE(hart) (VIRT_PLIC_BASE + PLIC_SCOMPLETE_OFFSET + (hart) * 0x1000)
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#endif
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#define PLIC_PRIORITY(id) (VIRT_PLIC_BASE + PLIC_PRIORITY_OFFSET + (id) * 4)
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#define PLIC_PENDING(id) (VIRT_PLIC_BASE + PLIC_PENDING_OFFSET + ((id) / 32))
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void plic_set_priority(int irq, int priority);
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void plic_irq_enable(int irq);
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void plic_irq_disable(int irq);
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void plic_set_threshold(int mthreshold);
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int plic_claim(void);
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void plic_complete(int irq);
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#endif
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