400 lines
13 KiB
C
400 lines
13 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_adc.h"
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#include "fsl_clock.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.lpc_adc"
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#endif
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static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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static uint32_t ADC_GetInstance(ADC_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++)
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{
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if (s_adcBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_adcBases));
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return instance;
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}
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void ADC_Init(ADC_Type *base, const adc_config_t *config)
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{
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assert(config != NULL);
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uint32_t tmp32 = 0U;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable clock. */
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CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Disable the interrupts. */
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base->INTEN = 0U; /* Quickly disable all the interrupts. */
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/* Configure the ADC block. */
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tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber);
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE
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/* Async or Sync clock mode. */
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switch (config->clockMode)
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{
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case kADC_ClockAsynchronousMode:
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tmp32 |= ADC_CTRL_ASYNMODE_MASK;
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break;
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default: /* kADC_ClockSynchronousMode */
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break;
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}
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#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL
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/* Resolution. */
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tmp32 |= ADC_CTRL_RESOL(config->resolution);
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL
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/* Bypass calibration. */
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if (config->enableBypassCalibration)
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{
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tmp32 |= ADC_CTRL_BYPASSCAL_MASK;
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}
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP
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/* Sample time clock count. */
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tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber);
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE
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if(config->enableLowPowerMode)
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{
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tmp32 |= ADC_CTRL_LPWRMODE_MASK;
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}
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */
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base->CTRL = tmp32;
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#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG
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base->TRM &= ~ADC_TRM_VRANGE_MASK;
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base->TRM |= ADC_TRM_VRANGE(config->voltageRange);
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#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */
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}
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void ADC_GetDefaultConfig(adc_config_t *config)
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{
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE
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config->clockMode = kADC_ClockSynchronousMode;
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */
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config->clockDividerNumber = 0U;
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL
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config->resolution = kADC_Resolution12bit;
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL
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config->enableBypassCalibration = false;
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP
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config->sampleTimeNumber = 0U;
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */
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#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE
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config->enableLowPowerMode = false;
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#endif/* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */
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#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG
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config->voltageRange = kADC_HighVoltageRange;
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#endif/* FSL_FEATURE_ADC_HAS_TRIM_REG. */
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}
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void ADC_Deinit(ADC_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the clock. */
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CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC)
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#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) & FSL_FEATURE_ADC_HAS_CALIB_REG
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bool ADC_DoSelfCalibration(ADC_Type *base)
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{
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uint32_t i;
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/* Enable the converter. */
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/* This bit acn only be set 1 by software. It is cleared automatically whenever the ADC is powered down.
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This bit should be set after at least 10 ms after the ADC is powered on. */
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base->STARTUP = ADC_STARTUP_ADC_ENA_MASK;
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for (i = 0U; i < 0x10; i++) /* Wait a few clocks to startup up. */
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{
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__ASM("NOP");
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}
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if (!(base->STARTUP & ADC_STARTUP_ADC_ENA_MASK))
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{
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return false; /* ADC is not powered up. */
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}
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/* If not in by-pass mode, do the calibration. */
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if ((ADC_CALIB_CALREQD_MASK == (base->CALIB & ADC_CALIB_CALREQD_MASK)) &&
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(0U == (base->CTRL & ADC_CTRL_BYPASSCAL_MASK)))
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{
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/* Calibration is needed, do it now. */
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base->CALIB = ADC_CALIB_CALIB_MASK;
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i = 0xF0000;
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while ((ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) && (--i))
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{
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}
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if (i == 0U)
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{
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return false; /* Calibration timeout. */
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}
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}
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/* A dummy conversion cycle will be performed. */
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base->STARTUP |= ADC_STARTUP_ADC_INIT_MASK;
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i = 0x7FFFF;
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while ((ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) && (--i))
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{
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}
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if (i == 0U)
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{
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return false;
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}
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return true;
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}
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#else
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bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency)
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{
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uint32_t tmp32;
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uint32_t i = 0xF0000;
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/* Store the current contents of the ADC CTRL register. */
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tmp32 = base->CTRL;
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/* Start ADC self-calibration. */
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base->CTRL |= ADC_CTRL_CALMODE_MASK;
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/* Divide the system clock to yield an ADC clock of about 500 kHz. */
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base->CTRL &= ~ADC_CTRL_CLKDIV_MASK;
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base->CTRL |= ADC_CTRL_CLKDIV((frequency / 500000U) - 1U);
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/* Clear the LPWR bit. */
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base->CTRL &= ~ADC_CTRL_LPWRMODE_MASK;
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/* Wait for the completion of calibration. */
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while ((ADC_CTRL_CALMODE_MASK == (base->CTRL & ADC_CTRL_CALMODE_MASK)) && (--i))
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{
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}
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/* Restore the contents of the ADC CTRL register. */
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base->CTRL = tmp32;
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/* Judge whether the calibration is overtime. */
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if (i == 0U)
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{
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return false; /* Calibration timeout. */
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}
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return true;
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}
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#endif/* FSL_FEATURE_ADC_HAS_CALIB_REG */
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#endif/* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC*/
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void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
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{
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assert(config != NULL);
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uint32_t tmp32;
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tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask) /* Channel mask. */
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| ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
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/* Polarity for tirgger signal. */
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switch (config->triggerPolarity)
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{
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case kADC_TriggerPolarityPositiveEdge:
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tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
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break;
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default: /* kADC_TriggerPolarityNegativeEdge */
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break;
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}
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/* Bypass the clock Sync. */
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if (config->enableSyncBypass)
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{
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tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
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}
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/* Interrupt point. */
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switch (config->interruptMode)
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{
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case kADC_InterruptForEachSequence:
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tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
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break;
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default: /* kADC_InterruptForEachConversion */
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break;
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}
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/* One trigger for a conversion, or for a sequence. */
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if (config->enableSingleStep)
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{
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tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
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}
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base->SEQ_CTRL[0] = tmp32;
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}
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void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
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{
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assert(config != NULL);
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uint32_t tmp32;
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tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask) /* Channel mask. */
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| ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
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/* Polarity for tirgger signal. */
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switch (config->triggerPolarity)
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{
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case kADC_TriggerPolarityPositiveEdge:
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tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
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break;
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default: /* kADC_TriggerPolarityPositiveEdge */
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break;
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}
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/* Bypass the clock Sync. */
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if (config->enableSyncBypass)
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{
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tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
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}
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/* Interrupt point. */
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switch (config->interruptMode)
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{
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case kADC_InterruptForEachSequence:
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tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
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break;
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default: /* kADC_InterruptForEachConversion */
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break;
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}
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/* One trigger for a conversion, or for a sequence. */
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if (config->enableSingleStep)
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{
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tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
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}
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base->SEQ_CTRL[1] = tmp32;
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}
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bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
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{
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assert(info != NULL);
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uint32_t tmp32 = base->SEQ_GDAT[0]; /* Read to clear the status. */
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if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
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{
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return false;
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}
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info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
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info->thresholdCompareStatus =
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(adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
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info->thresholdCorssingStatus =
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(adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
|
||
|
|
info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
|
||
|
|
info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
|
||
|
|
{
|
||
|
|
assert(info != NULL);
|
||
|
|
|
||
|
|
uint32_t tmp32 = base->SEQ_GDAT[1]; /* Read to clear the status. */
|
||
|
|
|
||
|
|
if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
|
||
|
|
{
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
|
||
|
|
info->thresholdCompareStatus =
|
||
|
|
(adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
|
||
|
|
info->thresholdCorssingStatus =
|
||
|
|
(adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
|
||
|
|
info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
|
||
|
|
info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info)
|
||
|
|
{
|
||
|
|
assert(info != NULL);
|
||
|
|
assert(channel < ADC_DAT_COUNT);
|
||
|
|
|
||
|
|
uint32_t tmp32 = base->DAT[channel]; /* Read to clear the status. */
|
||
|
|
|
||
|
|
if (0U == (ADC_DAT_DATAVALID_MASK & tmp32))
|
||
|
|
{
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
info->result = (tmp32 & ADC_DAT_RESULT_MASK) >> ADC_DAT_RESULT_SHIFT;
|
||
|
|
info->thresholdCompareStatus =
|
||
|
|
(adc_threshold_compare_status_t)((tmp32 & ADC_DAT_THCMPRANGE_MASK) >> ADC_DAT_THCMPRANGE_SHIFT);
|
||
|
|
info->thresholdCorssingStatus =
|
||
|
|
(adc_threshold_crossing_status_t)((tmp32 & ADC_DAT_THCMPCROSS_MASK) >> ADC_DAT_THCMPCROSS_SHIFT);
|
||
|
|
info->channelNumber = (tmp32 & ADC_DAT_CHANNEL_MASK) >> ADC_DAT_CHANNEL_SHIFT;
|
||
|
|
info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK);
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|