266 lines
5.2 KiB
ArmAsm
266 lines
5.2 KiB
ArmAsm
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/*
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* Copyright (c) 2018, Synopsys, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define __ASSEMBLY__
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#include "inc/arc/arc.h"
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#include "inc/arc/arc_asm_common.h"
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.global rt_interrupt_enter; .type rt_interrupt_enter, %function
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.global rt_interrupt_leave; .type rt_interrupt_leave, %function
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.global context_switch_reqflg; .type context_switch_reqflg, %object
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.global rt_interrupt_from_thread; .type rt_interrupt_from_thread, %object
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.global rt_interrupt_to_thread; .type rt_interrupt_to_thread, %object
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.text
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.align 4
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dispatcher:
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st sp, [r0]
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ld sp, [r1]
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pop r0
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j [r0]
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/* return routine when task dispatch happened in task context */
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dispatch_r:
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RESTORE_NONSCRATCH_REGS
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j [blink]
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.global rt_hw_interrupt_disable
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.type rt_hw_interrupt_disable, %function
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rt_hw_interrupt_disable:
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clri r0
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j [blink]
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.global rt_hw_interrupt_enable
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.type rt_hw_interrupt_enable, %function
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rt_hw_interrupt_enable:
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seti r0
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j [blink]
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.global rt_hw_context_switch_interrupt
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.type rt_hw_context_switch_interrupt, %function
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rt_hw_context_switch_interrupt:
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st r0, [rt_interrupt_from_thread]
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st r1, [rt_interrupt_to_thread]
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mov r0, 1
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st r0, [context_switch_reqflg]
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j [blink]
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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* r0 --> from
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* r1 --> to
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*/
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.global rt_hw_context_switch
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.type rt_hw_context_switch, %function
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rt_hw_context_switch:
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SAVE_NONSCRATCH_REGS
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mov r2, dispatch_r
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push r2
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b dispatcher
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* r0 --> to
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*/
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.global rt_hw_context_switch_to
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.type rt_hw_context_switch_to, %function
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rt_hw_context_switch_to:
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ld sp, [r0]
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pop r0
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j [r0]
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.global start_r
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.type start_r, %function
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start_r:
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pop blink;
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pop r1
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pop r2
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pop r0
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j_s.d [r1]
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kflag r2
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/****** exceptions and interrupts handing ******/
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/****** entry for exception handling ******/
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.global exc_entry_cpu
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.align 4
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exc_entry_cpu:
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EXCEPTION_PROLOGUE
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mov blink, sp
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mov r3, sp /* as exception handler's para(p_excinfo) */
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ld r0, [exc_nest_count]
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add r1, r0, 1
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st r1, [exc_nest_count]
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cmp r0, 0
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bne exc_handler_1
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/* change to exception stack if interrupt happened in task context */
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mov sp, _e_stack
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exc_handler_1:
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PUSH blink
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lr r0, [AUX_ECR]
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lsr r0, r0, 16
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mov r1, exc_int_handler_table
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ld.as r2, [r1, r0]
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mov r0, r3
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jl [r2]
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/* interrupts are not allowed */
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ret_exc:
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POP sp
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mov r1, exc_nest_count
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ld r0, [r1]
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sub r0, r0, 1
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cmp r0, 0
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bne.d ret_exc_1
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st r0, [r1]
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ld r0, [context_switch_reqflg]
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cmp r0, 0
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bne ret_exc_2
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ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */
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EXCEPTION_EPILOGUE
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rtie
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/* there is a dispatch request */
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ret_exc_2:
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/* clear dispatch request */
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mov r0, 0
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st r0, [context_switch_reqflg]
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SAVE_CALLEE_REGS /* save callee save registers */
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/* clear exception bit to do exception exit by SW */
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lr r0, [AUX_STATUS32]
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bclr r0, r0, AUX_STATUS_BIT_AE
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kflag r0
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mov r1, ret_exc_r /* save return address */
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PUSH r1
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ld r0, [rt_interrupt_from_thread]
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ld r1, [rt_interrupt_to_thread]
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b dispatcher
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ret_exc_r:
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/* recover exception status */
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lr r0, [AUX_STATUS32]
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bset r0, r0, AUX_STATUS_BIT_AE
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kflag r0
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RESTORE_CALLEE_REGS
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EXCEPTION_EPILOGUE
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rtie
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/****** entry for normal interrupt exception handling ******/
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.global exc_entry_int /* entry for interrupt handling */
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.align 4
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exc_entry_int:
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#if ARC_FEATURE_FIRQ == 1
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/* check whether it is P0 interrupt */
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#if ARC_FEATURE_RGF_NUM_BANKS > 1
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lr r0, [AUX_IRQ_ACT]
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btst r0, 0
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jnz exc_entry_firq
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#else
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PUSH r10
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lr r10, [AUX_IRQ_ACT]
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btst r10, 0
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POP r10
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jnz exc_entry_firq
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#endif
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#endif
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INTERRUPT_PROLOGUE
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mov blink, sp
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clri /* disable interrupt */
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ld r3, [exc_nest_count]
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add r2, r3, 1
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st r2, [exc_nest_count]
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seti /* enable higher priority interrupt */
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cmp r3, 0
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bne irq_handler_1
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/* change to exception stack if interrupt happened in task context */
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mov sp, _e_stack
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irq_handler_1:
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PUSH blink
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jl rt_interrupt_enter
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lr r0, [AUX_IRQ_CAUSE]
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sr r0, [AUX_IRQ_SELECT]
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mov r1, exc_int_handler_table
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ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */
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/* handle software triggered interrupt */
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lr r3, [AUX_IRQ_HINT]
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cmp r3, r0
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bne.d irq_hint_handled
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xor r3, r3, r3
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sr r3, [AUX_IRQ_HINT]
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irq_hint_handled:
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lr r3, [AUX_IRQ_PRIORITY]
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PUSH r3 /* save irq priority */
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jl [r2] /* jump to interrupt handler */
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jl rt_interrupt_leave
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ret_int:
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clri /* disable interrupt */
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POP r3 /* irq priority */
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POP sp
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mov r1, exc_nest_count
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ld r0, [r1]
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sub r0, r0, 1
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cmp r0, 0
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bne.d ret_int_1
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st r0, [r1]
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ld r0, [context_switch_reqflg]
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cmp r0, 0
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bne ret_int_2
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ret_int_1: /* return from non-task context */
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INTERRUPT_EPILOGUE
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rtie
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/* there is a dispatch request */
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ret_int_2:
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/* clear dispatch request */
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mov r0, 0
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st r0, [context_switch_reqflg]
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/* interrupt return by SW */
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lr r10, [AUX_IRQ_ACT]
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PUSH r10
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bclr r10, r10, r3 /* clear related bits in IRQ_ACT */
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sr r10, [AUX_IRQ_ACT]
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SAVE_CALLEE_REGS /* save callee save registers */
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mov r1, ret_int_r /* save return address */
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PUSH r1
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ld r0, [rt_interrupt_from_thread]
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ld r1, [rt_interrupt_to_thread]
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b dispatcher
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ret_int_r:
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RESTORE_CALLEE_REGS
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/* recover AUX_IRQ_ACT to restore the interrup status */
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POPAX AUX_IRQ_ACT
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INTERRUPT_EPILOGUE
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rtie
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