222 lines
6.6 KiB
C
222 lines
6.6 KiB
C
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022/12/25 flyingcys first version
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* 2023/01/17 chushicheng add pin and i2c
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* 2023/03/15 flyingcys update bsp file structure
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "drv_uart.h"
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#ifdef BSP_USING_SDH_SDCARD
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#include "sdh_sdcard.h"
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#endif
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static void system_clock_init(void)
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{
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/* wifipll/audiopll */
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GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL |
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GLB_PLL_CPUPLL |
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GLB_PLL_UHSPLL |
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GLB_PLL_MIPIPLL);
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GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_320M);
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GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_CPUPLL_400M);
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GLB_Config_CPU_PLL(GLB_XTAL_40M, cpuPllCfg_480M);
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CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
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}
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static void peripheral_clock_init(void)
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{
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PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
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PERIPHERAL_CLOCK_SEC_ENABLE();
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PERIPHERAL_CLOCK_DMA0_ENABLE();
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PERIPHERAL_CLOCK_UART0_ENABLE();
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PERIPHERAL_CLOCK_UART1_ENABLE();
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PERIPHERAL_CLOCK_SPI0_1_ENABLE();
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PERIPHERAL_CLOCK_I2C0_ENABLE();
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PERIPHERAL_CLOCK_PWM0_ENABLE();
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PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
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PERIPHERAL_CLOCK_IR_ENABLE();
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PERIPHERAL_CLOCK_I2S_ENABLE();
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PERIPHERAL_CLOCK_USB_ENABLE();
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PERIPHERAL_CLOCK_CAN_UART2_ENABLE();
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GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 4);
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GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0);
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GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_DSP_XCLK, 0);
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GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
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GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0);
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GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19);
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GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
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GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK);
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GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
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GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
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GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3);
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GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M);
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#ifdef BSP_USING_SDH_SDCARD
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PERIPHERAL_CLOCK_SDH_ENABLE();
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uint32_t tmp_val;
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tmp_val = BL_RD_REG(PDS_BASE, PDS_CTL5);
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uint32_t tmp_val2 = BL_GET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN);
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tmp_val2 &= ~(1 << 0);
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tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN, tmp_val2);
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BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val);
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GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SDH);
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#endif
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#ifdef BSP_USING_CSI
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GLB_CSI_Config_MIPIPLL(2, 0x21000);
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GLB_CSI_Power_Up_MIPIPLL();
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GLB_Set_DSP_CLK(ENABLE, GLB_DSP_CLK_MUXPLL_160M, 1);
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#endif
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GLB_Set_USB_CLK_From_WIFIPLL(1);
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}
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#ifdef BSP_USING_PSRAM
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#define WB_4MB_PSRAM (1)
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#define UHS_32MB_PSRAM (2)
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#define UHS_64MB_PSRAM (3)
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#define WB_32MB_PSRAM (4)
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#define NONE_UHS_PSRAM (-1)
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int uhs_psram_init(void)
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{
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PSRAM_UHS_Cfg_Type psramDefaultCfg = {
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2000,
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PSRAM_MEM_SIZE_32MB,
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PSRAM_PAGE_SIZE_2KB,
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PSRAM_UHS_NORMAL_TEMP,
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};
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bflb_efuse_device_info_type chip_info;
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bflb_ef_ctrl_get_device_info(&chip_info);
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if (chip_info.psramInfo == UHS_32MB_PSRAM) {
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psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_32MB;
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} else if (chip_info.psramInfo == UHS_64MB_PSRAM) {
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psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_64MB;
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} else {
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return -1;
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}
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//init uhs PLL; Must open uhs pll first, and then initialize uhs psram
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GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M);
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//init uhs psram ;
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// Psram_UHS_x16_Init(Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_PSRAMA) / 1000000);
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Psram_UHS_x16_Init_Override(&psramDefaultCfg);
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Tzc_Sec_PSRAMA_Access_Release();
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// example: 2000Mbps typical cal values
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uhs_phy_cal_res->rl = 39;
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uhs_phy_cal_res->rdqs = 3;
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uhs_phy_cal_res->rdq = 0;
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uhs_phy_cal_res->wl = 13;
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uhs_phy_cal_res->wdqs = 4;
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uhs_phy_cal_res->wdq = 5;
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uhs_phy_cal_res->ck = 9;
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/* TODO: use uhs psram trim update */
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set_uhs_latency_r(uhs_phy_cal_res->rl);
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cfg_dqs_rx(uhs_phy_cal_res->rdqs);
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cfg_dq_rx(uhs_phy_cal_res->rdq);
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set_uhs_latency_w(uhs_phy_cal_res->wl);
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cfg_dq_drv(uhs_phy_cal_res->wdq);
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cfg_ck_cen_drv(uhs_phy_cal_res->wdq + 4, uhs_phy_cal_res->wdq + 1);
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cfg_dqs_drv(uhs_phy_cal_res->wdqs);
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// set_odt_en();
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mr_read_back();
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return 0;
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}
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#endif
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/* This is the timer interrupt service routine. */
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static void systick_isr(void)
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{
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rt_tick_increase();
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}
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void rt_hw_board_init(void)
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{
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GLB_Halt_CPU(GLB_CORE_ID_D0);
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GLB_Halt_CPU(GLB_CORE_ID_LP);
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bflb_flash_init();
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system_clock_init();
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peripheral_clock_init();
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bflb_irq_initialize();
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bflb_mtimer_config(CPU_Get_MTimer_Clock() / RT_TICK_PER_SECOND, systick_isr);
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#ifdef RT_USING_HEAP
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/* initialize memory system */
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rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x size: %d\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END, RT_HW_HEAP_END - RT_HW_HEAP_BEGIN);
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rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
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#endif
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/* UART driver initialization is open by default */
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#ifdef RT_USING_SERIAL
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rt_hw_uart_init();
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#endif
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#ifdef BSP_USING_PSRAM
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if (uhs_psram_init() < 0)
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{
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rt_kprintf("uhs_psram_init failed!\n");
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}
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#endif
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/* GPIO driver initialization is open by default */
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#ifdef BSP_USING_PIN
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rt_hw_pin_init();
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#endif
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/* I2C driver initialization is open by default */
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#ifdef BSP_USING_I2C
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rt_hw_i2c_init();
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#endif
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/* Set the shell console output device */
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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/* set CPU D0 boot XIP address and flash address */
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Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
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/* D0 boot from 0x58000000 */
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GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
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/* D0 image offset on flash is CONFIG_D0_FLASH_ADDR+0x1000(header) */
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bflb_sf_ctrl_set_flash_image_offset(CONFIG_D0_FLASH_ADDR + 0x1000, 1, SF_CTRL_FLASH_BANK0);
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Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_LP, 0);
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/* LP boot from 0x580C0000 */
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GLB_Set_CPU_Reset_Address(GLB_CORE_ID_LP, 0x580C0000);
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GLB_Release_CPU(GLB_CORE_ID_D0);
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GLB_Release_CPU(GLB_CORE_ID_LP);
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/* release d0 and then do can run */
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BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG);
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BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG);
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L1C_DCache_Clean_By_Addr(IPC_SYNC_ADDR1, 8);
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}
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void rt_hw_cpu_reset(void)
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{
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GLB_SW_POR_Reset();
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}
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MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
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