120 lines
5.2 KiB
C
120 lines
5.2 KiB
C
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/*
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* Copyright (C) 2017-2019 Alibaba Group Holding Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 zx.chen CSI Core Peripheral Access Layer Header File for
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* CSKYSOC Device Series
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*/
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#ifndef _SOC_H_
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#define _SOC_H_
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#include <stdint.h>
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#include <csi_core.h>
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#include <sys_freq.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef IHS_VALUE
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#define IHS_VALUE (20000000)
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#endif
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#ifndef EHS_VALUE
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#define EHS_VALUE (20000000)
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#endif
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/* ------------------------- Interrupt Number Definition ------------------------ */
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typedef enum IRQn {
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NMI_EXPn = -2, /* NMI Exception */
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/* ---------------------- SmartL Specific Interrupt Numbers --------------------- */
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Machine_Software_IRQn = 3, /* Machine software interrupt */
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User_Timer_IRQn = 4, /* User timer interrupt */
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Supervisor_Timer_IRQn = 5, /* Supervisor timer interrupt */
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CORET_IRQn = 7, /* core Timer Interrupt */
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Machine_External_IRQn = 11, /* Machine external interrupt */
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UART_IRQn = 16, /* uart Interrupt */
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TIM0_IRQn = 18, /* timer0 Interrupt */
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TIM1_IRQn = 19, /* timer1 Interrupt */
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TIM2_IRQn = 20, /* timer2 Interrupt */
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TIM3_IRQn = 21, /* timer3 Interrupt */
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GPIO0_IRQn = 23, /* gpio0 Interrupt */
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GPIO1_IRQn = 24, /* gpio1 Interrupt */
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GPIO2_IRQn = 25, /* gpio2 Interrupt */
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GPIO3_IRQn = 26, /* gpio3 Interrupt */
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GPIO4_IRQn = 27, /* gpio4 Interrupt */
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GPIO5_IRQn = 28, /* gpio5 Interrupt */
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GPIO6_IRQn = 29, /* gpio6 Interrupt */
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GPIO7_IRQn = 30, /* gpio7 Interrupt */
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STIM0_IRQn = 31, /* stimer0 Interrupt */
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STIM1_IRQn = 32, /* stimer1 Interrupt */
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STIM2_IRQn = 33, /* stimer2 Interrupt */
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STIM3_IRQn = 34, /* stimer3 Interrupt */
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PAD_IRQn = 35, /* pad Interrupt */
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TIM6_IRQn = 36, /* timer6 Interrupt */
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TIM7_IRQn = 37, /* timer7 Interrupt */
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TIM8_IRQn = 38, /* timer8 Interrupt */
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TIM9_IRQn = 39, /* timer9 Interrupt */
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TIM10_IRQn = 40, /* timer10 Interrupt */
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TIM11_IRQn = 41, /* timer11 Interrupt */
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}
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IRQn_Type;
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/* ================================================================================ */
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/* ================ Device Specific Peripheral Section ================ */
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/* ================================================================================ */
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#define CONFIG_TIMER_NUM 12
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#define CONFIG_USART_NUM 1
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#define CONFIG_GPIO_NUM 8
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#define CONFIG_GPIO_PIN_NUM 8
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/* ================================================================================ */
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/* ================ Peripheral memory map ================ */
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/* ================================================================================ */
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/* -------------------------- CPU FPGA memory map ------------------------------- */
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#define CSKY_SRAM_BASE (0x20000000UL)
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#define CSKY_UART_BASE (0x40015000UL)
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#define CSKY_PMU_BASE (0x40016000UL)
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#define CSKY_TIMER0_BASE (0x40011000UL)
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#define CSKY_TIMER1_BASE (0x40011014UL)
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#define CSKY_TIMER2_BASE (0x40011028UL)
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#define CSKY_TIMER3_BASE (0x4001103cUL)
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#define CSKY_TIMER4_BASE (0x40021000UL)
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#define CSKY_TIMER5_BASE (0x40021014UL)
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#define CSKY_TIMER6_BASE (0x40021028UL)
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#define CSKY_TIMER7_BASE (0x4002103cUL)
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#define CSKY_TIMER8_BASE (0x40031000UL)
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#define CSKY_TIMER9_BASE (0x40031014UL)
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#define CSKY_TIMER10_BASE (0x40031028UL)
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#define CSKY_TIMER11_BASE (0x4003103cUL)
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#define CSKY_TIMER_CONTROL_BASE (0x400110a0UL)
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#define CSKY_CLK_GEN_BASE (0x40017000UL)
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#define CSKY_STIMER0_BASE (0x40018000UL)
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#define CSKY_STIMER1_BASE (0x40018014UL)
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#define CSKY_STIMER2_BASE (0x40018028UL)
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#define CSKY_STIMER3_BASE (0x4001803cUL)
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#define CSKY_STIMER_CONTROL_BASE (0x400110a0UL)
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#define CSKY_GPIOA_BASE (0x40019000UL)
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#define CSKY_GPIOA_CONTROL_BASE (0x40019030UL)
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#define CSKY_SMPU_BASE (0x4001a000UL)
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/* ================================================================================ */
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/* ================ Peripheral declaration ================ */
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/* ================================================================================ */
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#define CSKY_UART (( CSKY_UART_TypeDef *) CSKY_UART_BASE)
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_H_ */
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