141 lines
9.6 KiB
C
141 lines
9.6 KiB
C
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/**
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* \file
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*
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* \brief Instance description for RTC
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-31T14:29:25Z */
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#ifndef _SAML10_RTC_INSTANCE_H_
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#define _SAML10_RTC_INSTANCE_H_
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/* ========== Register definition for RTC peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_RTC_DBGCTRL (0x4000240E) /**< (RTC) Debug Control */
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#define REG_RTC_FREQCORR (0x40002414) /**< (RTC) Frequency Correction */
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#define REG_RTC_GP (0x40002440) /**< (RTC) General Purpose */
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#define REG_RTC_GP0 (0x40002440) /**< (RTC) General Purpose 0 */
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#define REG_RTC_GP1 (0x40002444) /**< (RTC) General Purpose 1 */
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#define REG_RTC_TAMPCTRL (0x40002460) /**< (RTC) Tamper Control */
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#define REG_RTC_TAMPID (0x40002468) /**< (RTC) Tamper ID */
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#define REG_RTC_TAMPCTRLB (0x4000246C) /**< (RTC) Tamper Control B */
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#define REG_RTC_MODE0_CTRLA (0x40002400) /**< (RTC) MODE0 Control A */
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#define REG_RTC_MODE0_CTRLB (0x40002402) /**< (RTC) MODE0 Control B */
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#define REG_RTC_MODE0_EVCTRL (0x40002404) /**< (RTC) MODE0 Event Control */
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#define REG_RTC_MODE0_INTENCLR (0x40002408) /**< (RTC) MODE0 Interrupt Enable Clear */
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#define REG_RTC_MODE0_INTENSET (0x4000240A) /**< (RTC) MODE0 Interrupt Enable Set */
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#define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< (RTC) MODE0 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< (RTC) MODE0 Synchronization Busy Status */
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#define REG_RTC_MODE0_COUNT (0x40002418) /**< (RTC) MODE0 Counter Value */
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#define REG_RTC_MODE0_COMP (0x40002420) /**< (RTC) MODE0 Compare n Value */
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#define REG_RTC_MODE0_COMP0 (0x40002420) /**< (RTC) MODE0 Compare 0 Value */
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#define REG_RTC_MODE0_TIMESTAMP (0x40002464) /**< (RTC) MODE0 Timestamp */
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#define REG_RTC_MODE1_CTRLA (0x40002400) /**< (RTC) MODE1 Control A */
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#define REG_RTC_MODE1_CTRLB (0x40002402) /**< (RTC) MODE1 Control B */
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#define REG_RTC_MODE1_EVCTRL (0x40002404) /**< (RTC) MODE1 Event Control */
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#define REG_RTC_MODE1_INTENCLR (0x40002408) /**< (RTC) MODE1 Interrupt Enable Clear */
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#define REG_RTC_MODE1_INTENSET (0x4000240A) /**< (RTC) MODE1 Interrupt Enable Set */
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#define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< (RTC) MODE1 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< (RTC) MODE1 Synchronization Busy Status */
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#define REG_RTC_MODE1_COUNT (0x40002418) /**< (RTC) MODE1 Counter Value */
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#define REG_RTC_MODE1_PER (0x4000241C) /**< (RTC) MODE1 Counter Period */
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#define REG_RTC_MODE1_COMP (0x40002420) /**< (RTC) MODE1 Compare n Value */
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#define REG_RTC_MODE1_COMP0 (0x40002420) /**< (RTC) MODE1 Compare 0 Value */
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#define REG_RTC_MODE1_COMP1 (0x40002422) /**< (RTC) MODE1 Compare 1 Value */
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#define REG_RTC_MODE1_TIMESTAMP (0x40002464) /**< (RTC) MODE1 Timestamp */
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#define REG_RTC_MODE2_ALARM0 (0x40002420) /**< (RTC) MODE2_ALARM Alarm 0 Value */
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#define REG_RTC_MODE2_MASK0 (0x40002424) /**< (RTC) MODE2_ALARM Alarm 0 Mask */
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#define REG_RTC_MODE2_CTRLA (0x40002400) /**< (RTC) MODE2 Control A */
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#define REG_RTC_MODE2_CTRLB (0x40002402) /**< (RTC) MODE2 Control B */
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#define REG_RTC_MODE2_EVCTRL (0x40002404) /**< (RTC) MODE2 Event Control */
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#define REG_RTC_MODE2_INTENCLR (0x40002408) /**< (RTC) MODE2 Interrupt Enable Clear */
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#define REG_RTC_MODE2_INTENSET (0x4000240A) /**< (RTC) MODE2 Interrupt Enable Set */
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#define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< (RTC) MODE2 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< (RTC) MODE2 Synchronization Busy Status */
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#define REG_RTC_MODE2_CLOCK (0x40002418) /**< (RTC) MODE2 Clock Value */
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#define REG_RTC_MODE2_TIMESTAMP (0x40002464) /**< (RTC) MODE2 Timestamp */
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#else
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#define REG_RTC_DBGCTRL (*(__IO uint8_t*)0x4000240EU) /**< (RTC) Debug Control */
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#define REG_RTC_FREQCORR (*(__IO uint8_t*)0x40002414U) /**< (RTC) Frequency Correction */
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#define REG_RTC_GP (*(__IO uint32_t*)0x40002440U) /**< (RTC) General Purpose */
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#define REG_RTC_GP0 (*(__IO uint32_t*)0x40002440U) /**< (RTC) General Purpose 0 */
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#define REG_RTC_GP1 (*(__IO uint32_t*)0x40002444U) /**< (RTC) General Purpose 1 */
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#define REG_RTC_TAMPCTRL (*(__IO uint32_t*)0x40002460U) /**< (RTC) Tamper Control */
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#define REG_RTC_TAMPID (*(__IO uint32_t*)0x40002468U) /**< (RTC) Tamper ID */
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#define REG_RTC_TAMPCTRLB (*(__IO uint32_t*)0x4000246CU) /**< (RTC) Tamper Control B */
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#define REG_RTC_MODE0_CTRLA (*(__IO uint16_t*)0x40002400U) /**< (RTC) MODE0 Control A */
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#define REG_RTC_MODE0_CTRLB (*(__IO uint16_t*)0x40002402U) /**< (RTC) MODE0 Control B */
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#define REG_RTC_MODE0_EVCTRL (*(__IO uint32_t*)0x40002404U) /**< (RTC) MODE0 Event Control */
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#define REG_RTC_MODE0_INTENCLR (*(__IO uint16_t*)0x40002408U) /**< (RTC) MODE0 Interrupt Enable Clear */
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#define REG_RTC_MODE0_INTENSET (*(__IO uint16_t*)0x4000240AU) /**< (RTC) MODE0 Interrupt Enable Set */
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#define REG_RTC_MODE0_INTFLAG (*(__IO uint16_t*)0x4000240CU) /**< (RTC) MODE0 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE0_SYNCBUSY (*(__I uint32_t*)0x40002410U) /**< (RTC) MODE0 Synchronization Busy Status */
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#define REG_RTC_MODE0_COUNT (*(__IO uint32_t*)0x40002418U) /**< (RTC) MODE0 Counter Value */
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#define REG_RTC_MODE0_COMP (*(__IO uint32_t*)0x40002420U) /**< (RTC) MODE0 Compare n Value */
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#define REG_RTC_MODE0_COMP0 (*(__IO uint32_t*)0x40002420U) /**< (RTC) MODE0 Compare 0 Value */
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#define REG_RTC_MODE0_TIMESTAMP (*(__I uint32_t*)0x40002464U) /**< (RTC) MODE0 Timestamp */
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#define REG_RTC_MODE1_CTRLA (*(__IO uint16_t*)0x40002400U) /**< (RTC) MODE1 Control A */
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#define REG_RTC_MODE1_CTRLB (*(__IO uint16_t*)0x40002402U) /**< (RTC) MODE1 Control B */
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#define REG_RTC_MODE1_EVCTRL (*(__IO uint32_t*)0x40002404U) /**< (RTC) MODE1 Event Control */
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#define REG_RTC_MODE1_INTENCLR (*(__IO uint16_t*)0x40002408U) /**< (RTC) MODE1 Interrupt Enable Clear */
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#define REG_RTC_MODE1_INTENSET (*(__IO uint16_t*)0x4000240AU) /**< (RTC) MODE1 Interrupt Enable Set */
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#define REG_RTC_MODE1_INTFLAG (*(__IO uint16_t*)0x4000240CU) /**< (RTC) MODE1 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE1_SYNCBUSY (*(__I uint32_t*)0x40002410U) /**< (RTC) MODE1 Synchronization Busy Status */
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#define REG_RTC_MODE1_COUNT (*(__IO uint16_t*)0x40002418U) /**< (RTC) MODE1 Counter Value */
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#define REG_RTC_MODE1_PER (*(__IO uint16_t*)0x4000241CU) /**< (RTC) MODE1 Counter Period */
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#define REG_RTC_MODE1_COMP (*(__IO uint16_t*)0x40002420U) /**< (RTC) MODE1 Compare n Value */
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#define REG_RTC_MODE1_COMP0 (*(__IO uint16_t*)0x40002420U) /**< (RTC) MODE1 Compare 0 Value */
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#define REG_RTC_MODE1_COMP1 (*(__IO uint16_t*)0x40002422U) /**< (RTC) MODE1 Compare 1 Value */
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#define REG_RTC_MODE1_TIMESTAMP (*(__I uint32_t*)0x40002464U) /**< (RTC) MODE1 Timestamp */
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#define REG_RTC_MODE2_ALARM0 (*(__IO uint32_t*)0x40002420U) /**< (RTC) MODE2_ALARM Alarm 0 Value */
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#define REG_RTC_MODE2_MASK0 (*(__IO uint8_t*)0x40002424U) /**< (RTC) MODE2_ALARM Alarm 0 Mask */
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#define REG_RTC_MODE2_CTRLA (*(__IO uint16_t*)0x40002400U) /**< (RTC) MODE2 Control A */
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#define REG_RTC_MODE2_CTRLB (*(__IO uint16_t*)0x40002402U) /**< (RTC) MODE2 Control B */
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#define REG_RTC_MODE2_EVCTRL (*(__IO uint32_t*)0x40002404U) /**< (RTC) MODE2 Event Control */
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#define REG_RTC_MODE2_INTENCLR (*(__IO uint16_t*)0x40002408U) /**< (RTC) MODE2 Interrupt Enable Clear */
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#define REG_RTC_MODE2_INTENSET (*(__IO uint16_t*)0x4000240AU) /**< (RTC) MODE2 Interrupt Enable Set */
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#define REG_RTC_MODE2_INTFLAG (*(__IO uint16_t*)0x4000240CU) /**< (RTC) MODE2 Interrupt Flag Status and Clear */
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#define REG_RTC_MODE2_SYNCBUSY (*(__I uint32_t*)0x40002410U) /**< (RTC) MODE2 Synchronization Busy Status */
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#define REG_RTC_MODE2_CLOCK (*(__IO uint32_t*)0x40002418U) /**< (RTC) MODE2 Clock Value */
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#define REG_RTC_MODE2_TIMESTAMP (*(__I uint32_t*)0x40002464U) /**< (RTC) MODE2 Timestamp */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for RTC peripheral ========== */
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#define RTC_DMAC_ID_TIMESTAMP 1 /* DMA RTC timestamp trigger */
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#define RTC_GPR_NUM 2 /* Number of General-Purpose Registers */
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#define RTC_NUM_OF_ALARMS 1 /* Number of Alarms */
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#define RTC_NUM_OF_BKREGS 0 /* Number of Backup Registers */
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#define RTC_NUM_OF_COMP16 2 /* Number of 16-bit Comparators */
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#define RTC_NUM_OF_COMP32 1 /* Number of 32-bit Comparators */
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#define RTC_NUM_OF_TAMPERS 4 /* Number of Tamper Inputs */
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#define RTC_PER_NUM 8 /* Number of Periodic Intervals */
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#define RTC_INSTANCE_ID 9
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#endif /* _SAML10_RTC_INSTANCE_ */
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