465 lines
19 KiB
C
465 lines
19 KiB
C
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/*
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* File : code_run.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERsrcANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* srcange Logs:
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* Date Author Notes
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* 2018-07-05 ZYH the first version
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*/
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#include <rtthread.h>
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#define PRINTF rt_kprintf
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#include "board.h"
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#include <rthw.h>
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#include "drv_flexspi.h"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME "[Hyper]"
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#define DBG_LEVEL DBG_LOG
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#define DBG_COLOR
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#include <rtdbg.h>
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#define FLEXSPI_CLOCK kCLOCK_FlexSpi
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#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0
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#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1
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#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2
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#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4
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#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6
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#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10
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#define CUSTOM_LUT_LENGTH 48
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static flexspi_device_config_t deviceconfig = {
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.flexspiRootClk = 42000000, /* 42MHZ SPI serial clock */
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.isSck2Enabled = false,
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.flashSize = FLASH_SIZE,
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.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
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.CSInterval = 2,
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.CSHoldTime = 0,
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.CSSetupTime = 3,
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.dataValidTime = 1,
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.columnspace = 3,
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.enableWordAddress = true,
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.AWRSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA,
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.AWRSeqNumber = 1,
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.ARDSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA,
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.ARDSeqNumber = 1,
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.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
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.AHBWriteWaitInterval = 20,
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};
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static uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
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/* Read Data */
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
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/* Write Data */
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02),
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/* Read Status */
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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/* Write Enable */
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
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/* Erase Sector */
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
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/* program page */
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
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[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80),
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};
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SECTION("itcm") status_t flexspi_nor_hyperbus_read(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes)
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{
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flexspi_transfer_t flashXfer;
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status_t status;
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flashXfer.deviceAddress = addr * 2;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Read;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA;
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flashXfer.data = buffer;
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flashXfer.dataSize = bytes;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success)
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{
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return status;
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}
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return status;
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}
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SECTION("itcm") status_t flexspi_nor_hyperbus_write(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes)
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{
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flexspi_transfer_t flashXfer;
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status_t status;
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flashXfer.deviceAddress = addr * 2;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Write;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA;
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flashXfer.data = buffer;
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flashXfer.dataSize = bytes;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success)
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{
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return status;
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}
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return status;
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}
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SECTION("itcm") status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr)
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{
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flexspi_transfer_t flashXfer;
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status_t status;
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/* Write neable */
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flashXfer.deviceAddress = baseAddr;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 2;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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return status;
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}
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SECTION("itcm") status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base)
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{
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/* Wait status ready. */
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bool isBusy;
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uint32_t readValue;
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status_t status;
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flexspi_transfer_t flashXfer;
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Read;
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flashXfer.SeqNumber = 2;
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flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS;
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flashXfer.data = &readValue;
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flashXfer.dataSize = 2;
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do
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{
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success)
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{
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return status;
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}
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if (readValue & 0x8000)
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{
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isBusy = false;
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}
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else
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{
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isBusy = true;
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}
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if (readValue & 0x3200)
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{
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status = kStatus_Fail;
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break;
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|
|
}
|
||
|
|
|
||
|
|
} while (isBusy);
|
||
|
|
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address)
|
||
|
|
{
|
||
|
|
status_t status;
|
||
|
|
flexspi_transfer_t flashXfer;
|
||
|
|
rt_uint32_t level;
|
||
|
|
level = rt_hw_interrupt_disable();
|
||
|
|
FLEXSPI_Enable(FLEXSPI, false);
|
||
|
|
CLOCK_DisableClock(FLEXSPI_CLOCK);
|
||
|
|
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */
|
||
|
|
CLOCK_EnableClock(FLEXSPI_CLOCK);
|
||
|
|
FLEXSPI_Enable(FLEXSPI, true);
|
||
|
|
/* Write enable */
|
||
|
|
status = flexspi_nor_write_enable(base, address);
|
||
|
|
|
||
|
|
if (status != kStatus_Success)
|
||
|
|
{
|
||
|
|
FLEXSPI_Enable(FLEXSPI, false);
|
||
|
|
CLOCK_DisableClock(FLEXSPI_CLOCK);
|
||
|
|
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
|
||
|
|
CLOCK_EnableClock(FLEXSPI_CLOCK);
|
||
|
|
FLEXSPI_Enable(FLEXSPI, true);
|
||
|
|
FLEXSPI_SoftwareReset(FLEXSPI);
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
flashXfer.deviceAddress = address;
|
||
|
|
flashXfer.port = kFLEXSPI_PortA1;
|
||
|
|
flashXfer.cmdType = kFLEXSPI_Command;
|
||
|
|
flashXfer.SeqNumber = 4;
|
||
|
|
flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR;
|
||
|
|
status = FLEXSPI_TransferBlocking(base, &flashXfer);
|
||
|
|
|
||
|
|
if (status != kStatus_Success)
|
||
|
|
{
|
||
|
|
FLEXSPI_Enable(FLEXSPI, false);
|
||
|
|
CLOCK_DisableClock(FLEXSPI_CLOCK);
|
||
|
|
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
|
||
|
|
CLOCK_EnableClock(FLEXSPI_CLOCK);
|
||
|
|
FLEXSPI_Enable(FLEXSPI, true);
|
||
|
|
FLEXSPI_SoftwareReset(FLEXSPI);
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
status = flexspi_nor_wait_bus_busy(base);
|
||
|
|
rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE);
|
||
|
|
rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE);
|
||
|
|
FLEXSPI_Enable(FLEXSPI, false);
|
||
|
|
CLOCK_DisableClock(FLEXSPI_CLOCK);
|
||
|
|
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
|
||
|
|
CLOCK_EnableClock(FLEXSPI_CLOCK);
|
||
|
|
FLEXSPI_Enable(FLEXSPI, true);
|
||
|
|
FLEXSPI_SoftwareReset(FLEXSPI);
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src)
|
||
|
|
{
|
||
|
|
status_t status;
|
||
|
|
flexspi_transfer_t flashXfer;
|
||
|
|
rt_uint32_t level;
|
||
|
|
level = rt_hw_interrupt_disable();
|
||
|
|
FLEXSPI_Enable(FLEXSPI, false);
|
||
|
|
CLOCK_DisableClock(FLEXSPI_CLOCK);
|
||
|
|
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */
|
||
|
|
CLOCK_EnableClock(FLEXSPI_CLOCK);
|
||
|
|
FLEXSPI_Enable(FLEXSPI, true);
|
||
|
|
/* Write neable */
|
||
|
|
status = flexspi_nor_write_enable(base, address);
|
||
|
|
|
||
|
|
if (status != kStatus_Success)
|
||
|
|
{
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Prepare page program command */
|
||
|
|
flashXfer.deviceAddress = address;
|
||
|
|
flashXfer.port = kFLEXSPI_PortA1;
|
||
|
|
flashXfer.cmdType = kFLEXSPI_Write;
|
||
|
|
flashXfer.SeqNumber = 2;
|
||
|
|
flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
|
||
|
|
flashXfer.data = (uint32_t *)src;
|
||
|
|
flashXfer.dataSize = FLASH_PAGE_SIZE;
|
||
|
|
status = FLEXSPI_TransferBlocking(base, &flashXfer);
|
||
|
|
|
||
|
|
if (status != kStatus_Success)
|
||
|
|
{
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
status = flexspi_nor_wait_bus_busy(base);
|
||
|
|
|
||
|
|
rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE);
|
||
|
|
rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE);
|
||
|
|
FLEXSPI_Enable(FLEXSPI, false);
|
||
|
|
CLOCK_DisableClock(FLEXSPI_CLOCK);
|
||
|
|
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
|
||
|
|
CLOCK_EnableClock(FLEXSPI_CLOCK);
|
||
|
|
FLEXSPI_Enable(FLEXSPI, true);
|
||
|
|
FLEXSPI_SoftwareReset(FLEXSPI);
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
SECTION("itcm") status_t flexspi_nor_hyperflash_cfi(FLEXSPI_Type *base)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* Read ID-CFI Parameters
|
||
|
|
*/
|
||
|
|
// CFI Entry
|
||
|
|
status_t status;
|
||
|
|
uint32_t buffer[2];
|
||
|
|
uint32_t data = 0x9800;
|
||
|
|
status = flexspi_nor_hyperbus_write(base, 0x555, &data, 2);
|
||
|
|
if (status != kStatus_Success)
|
||
|
|
{
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
// ID-CFI Read
|
||
|
|
// Read Query Unique ASCII String
|
||
|
|
status = flexspi_nor_hyperbus_read(base, 0x10, &buffer[0], sizeof(buffer));
|
||
|
|
if (status != kStatus_Success)
|
||
|
|
{
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
buffer[1] &= 0xFFFF;
|
||
|
|
// Check that the data read out is unicode "QRY" in big-endian order
|
||
|
|
if ((buffer[0] != 0x52005100) || (buffer[1] != 0x5900))
|
||
|
|
{
|
||
|
|
status = kStatus_Fail;
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
// ASO Exit
|
||
|
|
data = 0xF000;
|
||
|
|
status = flexspi_nor_hyperbus_write(base, 0x0, &data, 2);
|
||
|
|
if (status != kStatus_Success)
|
||
|
|
{
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
SECTION("itcm") int rt_hw_flexspi_init(void)
|
||
|
|
{
|
||
|
|
flexspi_config_t config;
|
||
|
|
status_t status;
|
||
|
|
rt_uint32_t level;
|
||
|
|
level = rt_hw_interrupt_disable();
|
||
|
|
// Set flexspi root clock to 166MHZ.
|
||
|
|
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
|
||
|
|
|
||
|
|
CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
|
||
|
|
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 26); /* Set PLL3 PFD0 clock 332MHZ. */
|
||
|
|
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
|
||
|
|
|
||
|
|
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 83M, DDR mode, internal clock 42M. */
|
||
|
|
|
||
|
|
|
||
|
|
/*Get FLEXSPI default settings and configure the flexspi. */
|
||
|
|
FLEXSPI_GetDefaultConfig(&config);
|
||
|
|
|
||
|
|
/*Set AHB buffer size for reading data through AHB bus. */
|
||
|
|
config.ahbConfig.enableAHBPrefetch = true;
|
||
|
|
/*Allow AHB read start address do not follow the alignment requirement. */
|
||
|
|
config.ahbConfig.enableReadAddressOpt = true;
|
||
|
|
/* enable diff clock and DQS */
|
||
|
|
config.enableSckBDiffOpt = true;
|
||
|
|
config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
|
||
|
|
config.enableCombination = true;
|
||
|
|
FLEXSPI_Init(FLEXSPI, &config);
|
||
|
|
|
||
|
|
/* Configure flash settings according to serial flash feature. */
|
||
|
|
FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
|
||
|
|
|
||
|
|
/* Update LUT table. */
|
||
|
|
FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
|
||
|
|
|
||
|
|
/* Do software reset. */
|
||
|
|
FLEXSPI_SoftwareReset(FLEXSPI);
|
||
|
|
|
||
|
|
status = flexspi_nor_hyperflash_cfi(FLEXSPI);
|
||
|
|
/* Get vendor ID. */
|
||
|
|
if (status != kStatus_Success)
|
||
|
|
{
|
||
|
|
FLEXSPI_Enable(FLEXSPI, false);
|
||
|
|
CLOCK_DisableClock(FLEXSPI_CLOCK);
|
||
|
|
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
|
||
|
|
CLOCK_EnableClock(FLEXSPI_CLOCK);
|
||
|
|
FLEXSPI_Enable(FLEXSPI, true);
|
||
|
|
FLEXSPI_SoftwareReset(FLEXSPI);
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
FLEXSPI_Enable(FLEXSPI, false);
|
||
|
|
CLOCK_DisableClock(FLEXSPI_CLOCK);
|
||
|
|
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
|
||
|
|
CLOCK_EnableClock(FLEXSPI_CLOCK);
|
||
|
|
FLEXSPI_Enable(FLEXSPI, true);
|
||
|
|
FLEXSPI_SoftwareReset(FLEXSPI);
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
INIT_PREV_EXPORT(rt_hw_flexspi_init);
|