296 lines
9.1 KiB
C
296 lines
9.1 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_cmp.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.cmp"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for CMP module.
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*
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* @param base CMP peripheral base address
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*/
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static uint32_t CMP_GetInstance(CMP_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to CMP bases for each instance. */
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static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to CMP clocks for each instance. */
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static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Codes
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******************************************************************************/
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static uint32_t CMP_GetInstance(CMP_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_cmpBases); instance++)
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{
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if (s_cmpBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_cmpBases));
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return instance;
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}
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void CMP_Init(CMP_Type *base, const cmp_config_t *config)
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{
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assert(NULL != config);
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uint8_t tmp8;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Configure. */
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CMP_Enable(base, false); /* Disable the CMP module during configuring. */
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/* CMPx_CR1. */
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tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK);
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if (config->enableHighSpeed)
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{
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tmp8 |= CMP_CR1_PMODE_MASK;
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}
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if (config->enableInvertOutput)
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{
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tmp8 |= CMP_CR1_INV_MASK;
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}
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if (config->useUnfilteredOutput)
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{
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tmp8 |= CMP_CR1_COS_MASK;
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}
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if (config->enablePinOut)
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{
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tmp8 |= CMP_CR1_OPE_MASK;
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}
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#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
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if (config->enableTriggerMode)
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{
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tmp8 |= CMP_CR1_TRIGM_MASK;
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}
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else
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{
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tmp8 &= ~CMP_CR1_TRIGM_MASK;
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}
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#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
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base->CR1 = tmp8;
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/* CMPx_CR0. */
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tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK;
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tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode);
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base->CR0 = tmp8;
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CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */
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}
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void CMP_Deinit(CMP_Type *base)
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{
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/* Disable the CMP module. */
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CMP_Enable(base, false);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the clock. */
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CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void CMP_GetDefaultConfig(cmp_config_t *config)
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{
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assert(NULL != config);
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config->enableCmp = true; /* Enable the CMP module after initialization. */
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config->hysteresisMode = kCMP_HysteresisLevel0;
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config->enableHighSpeed = false;
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config->enableInvertOutput = false;
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config->useUnfilteredOutput = false;
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config->enablePinOut = false;
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#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
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config->enableTriggerMode = false;
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#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */
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}
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void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel)
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{
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uint8_t tmp8 = base->MUXCR;
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tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK);
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tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel);
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base->MUXCR = tmp8;
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}
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#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA
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void CMP_EnableDMA(CMP_Type *base, bool enable)
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{
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uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
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if (enable)
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{
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tmp8 |= CMP_SCR_DMAEN_MASK;
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}
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else
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{
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tmp8 &= ~CMP_SCR_DMAEN_MASK;
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}
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base->SCR = tmp8;
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}
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#endif /* FSL_FEATURE_CMP_HAS_DMA */
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void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config)
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{
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assert(NULL != config);
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uint8_t tmp8;
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#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
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/* Choose the clock source for sampling. */
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if (config->enableSample)
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{
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base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */
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}
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else
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{
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base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */
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}
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#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
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/* Set the filter count. */
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tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK;
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tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount);
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base->CR0 = tmp8;
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/* Set the filter period. It is used as the divider to bus clock. */
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base->FPR = CMP_FPR_FILT_PER(config->filterPeriod);
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}
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void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
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{
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uint8_t tmp8 = 0U;
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if (NULL == config)
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{
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/* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/
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base->DACCR = 0U;
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return;
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}
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/* CMPx_DACCR. */
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tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */
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if (kCMP_VrefSourceVin2 == config->referenceVoltageSource)
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{
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tmp8 |= CMP_DACCR_VRSEL_MASK;
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}
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tmp8 |= CMP_DACCR_VOSEL(config->DACValue);
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base->DACCR = tmp8;
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}
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void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask)
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{
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uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
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if (0U != (kCMP_OutputRisingInterruptEnable & mask))
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{
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tmp8 |= CMP_SCR_IER_MASK;
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}
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if (0U != (kCMP_OutputFallingInterruptEnable & mask))
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{
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tmp8 |= CMP_SCR_IEF_MASK;
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}
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base->SCR = tmp8;
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}
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void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask)
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{
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uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
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if (0U != (kCMP_OutputRisingInterruptEnable & mask))
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{
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tmp8 &= ~CMP_SCR_IER_MASK;
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}
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if (0U != (kCMP_OutputFallingInterruptEnable & mask))
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{
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tmp8 &= ~CMP_SCR_IEF_MASK;
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}
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base->SCR = tmp8;
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}
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uint32_t CMP_GetStatusFlags(CMP_Type *base)
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{
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uint32_t ret32 = 0U;
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if (0U != (CMP_SCR_CFR_MASK & base->SCR))
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{
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ret32 |= kCMP_OutputRisingEventFlag;
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}
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if (0U != (CMP_SCR_CFF_MASK & base->SCR))
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{
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ret32 |= kCMP_OutputFallingEventFlag;
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}
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if (0U != (CMP_SCR_COUT_MASK & base->SCR))
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{
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ret32 |= kCMP_OutputAssertEventFlag;
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}
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return ret32;
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}
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void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask)
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{
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uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */
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if (0U != (kCMP_OutputRisingEventFlag & mask))
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{
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tmp8 |= CMP_SCR_CFR_MASK;
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}
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if (0U != (kCMP_OutputFallingEventFlag & mask))
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{
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tmp8 |= CMP_SCR_CFF_MASK;
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}
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base->SCR = tmp8;
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}
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