292 lines
7.2 KiB
C
292 lines
7.2 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-1-13 Leo first version
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*/
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#include <board.h>
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#include "drv_pwm.h"
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#ifdef RT_USING_PWM
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#if !defined(BSP_USING_TMR1_CH1) && !defined(BSP_USING_TMR1_CH2) && \
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!defined(BSP_USING_TMR1_CH3) && !defined(BSP_USING_TMR1_CH4) && \
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!defined(BSP_USING_TMR2_CH1) && !defined(BSP_USING_TMR2_CH4) && \
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!defined(BSP_USING_TMR2_CH3) && !defined(BSP_USING_TMR3_CH2) && \
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!defined(BSP_USING_TMR3_CH1) && !defined(BSP_USING_TMR1_CH4) && \
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!defined(BSP_USING_TMR3_CH3) && !defined(BSP_USING_TMR3_CH4)
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#error "Please define at least one BSP_USING_TMRx_CHx"
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#endif
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#endif /* RT_USING_PWM */
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#define DRV_DEBUG
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#define LOG_TAG "drv.pwm"
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#include <drv_log.h>
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#define MAX_PERIOD 65535
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struct rt_device_pwm pwm_device;
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struct at32_pwm
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{
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struct rt_device_pwm pwm_device;
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TMR_Type* tim_handle;
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rt_uint8_t channel;
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char *name;
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};
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static struct at32_pwm at32_pwm_obj[] =
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{
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#ifdef BSP_USING_TMR1_CH1
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PWM1_CONFIG,
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#endif
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#ifdef BSP_USING_TMR1_CH2
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PWM2_CONFIG,
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#endif
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#ifdef BSP_USING_TMR1_CH3
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PWM3_CONFIG,
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#endif
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#ifdef BSP_USING_TMR1_CH4
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PWM4_CONFIG,
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#endif
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#ifdef BSP_USING_TMR2_CH1
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PWM5_CONFIG,
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#endif
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#ifdef BSP_USING_TMR2_CH2
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PWM6_CONFIG,
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#endif
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#ifdef BSP_USING_TMR2_CH3
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PWM7_CONFIG,
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#endif
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#ifdef BSP_USING_TMR2_CH4
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PWM8_CONFIG,
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#endif
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#ifdef BSP_USING_TMR3_CH1
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PWM9_CONFIG,
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#endif
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#ifdef BSP_USING_TMR3_CH2
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PWM10_CONFIG,
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#endif
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#ifdef BSP_USING_TMR3_CH3
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PWM11_CONFIG,
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#endif
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#ifdef BSP_USING_TMR3_CH4
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PWM12_CONFIG,
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#endif
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};
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
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static struct rt_pwm_ops drv_ops =
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{
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drv_pwm_control
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};
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static rt_err_t drv_pwm_enable(TMR_Type* TMRx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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/* Get the value of channel */
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rt_uint32_t channel = configuration->channel;
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if (!enable)
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{
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if(channel == 1)
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{
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TMR_CCxCmd(TMRx, TMR_Channel_1, TMR_CCx_Disable);
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}
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else if(channel == 2)
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{
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TMR_CCxCmd(TMRx, TMR_Channel_2, TMR_CCx_Disable);
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}
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else if(channel == 3)
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{
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TMR_CCxCmd(TMRx, TMR_Channel_3, TMR_CCx_Disable);
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}
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else if(channel == 4)
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{
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TMR_CCxCmd(TMRx, TMR_Channel_4, TMR_CCx_Disable);
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}
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}
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else
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{
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if(channel == 1)
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{
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TMR_CCxCmd(TMRx, TMR_Channel_1, TMR_CCx_Enable);
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}
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else if(channel == 2)
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{
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TMR_CCxCmd(TMRx, TMR_Channel_1, TMR_CCx_Enable);
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}
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else if(channel == 3)
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{
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TMR_CCxCmd(TMRx, TMR_Channel_1, TMR_CCx_Enable);
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}
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else if(channel == 4)
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{
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TMR_CCxCmd(TMRx, TMR_Channel_1, TMR_CCx_Enable);
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}
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}
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/* TMRx enable counter */
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TMR_Cmd(TMRx, ENABLE);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_get(TMR_Type* TMRx, struct rt_pwm_configuration *configuration)
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{
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RCC_ClockType RCC_Clockstruct;
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rt_uint32_t ar, div, cc1, cc2, cc3, cc4;
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rt_uint32_t channel = configuration->channel;
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rt_uint64_t tim_clock;
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ar = TMRx->AR;
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div = TMRx->DIV;
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cc1 = TMRx->CC1;
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cc2 = TMRx->CC2;
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cc3 = TMRx->CC3;
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cc4 = TMRx->CC4;
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RCC_GetClocksFreq(&RCC_Clockstruct);
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tim_clock = RCC_Clockstruct.APB2CLK_Freq;
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/* Convert nanosecond to frequency and duty cycle. */
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tim_clock /= 1000000UL;
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configuration->period = (ar + 1) * (div + 1) * 1000UL / tim_clock;
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if(channel == 1)
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configuration->pulse = (cc1 + 1) * (div + 1) * 1000UL / tim_clock;
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if(channel == 2)
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configuration->pulse = (cc2 + 1) * (div+ 1) * 1000UL / tim_clock;
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if(channel == 3)
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configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock;
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if(channel == 4)
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configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock;
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configuration)
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{
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TMR_TimerBaseInitType TMR_TMReBaseStructure;
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TMR_OCInitType TMR_OCInitStructure;
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rt_uint32_t period, pulse;
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rt_uint64_t psc;
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/* Get the channel number */
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rt_uint32_t channel = configuration->channel;
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/* Init timer pin and enable clock */
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at32_msp_tmr_init(TMRx);
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/* Convert nanosecond to frequency and duty cycle. */
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period = (unsigned long long)configuration->period ;
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psc = period / MAX_PERIOD + 1;
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period = period / psc;
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/* TMRe base configuration */
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TMR_TimeBaseStructInit(&TMR_TMReBaseStructure);
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TMR_TMReBaseStructure.TMR_Period = period;
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TMR_TMReBaseStructure.TMR_DIV = psc - 1;
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TMR_TMReBaseStructure.TMR_ClockDivision = 0;
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TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Up;
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TMR_TimeBaseInit(TMRx, &TMR_TMReBaseStructure);
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pulse = (unsigned long long)configuration->pulse;
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/* PWM1 Mode configuration: Channel1 */
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TMR_OCStructInit(&TMR_OCInitStructure);
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TMR_OCInitStructure.TMR_OCMode = TMR_OCMode_PWM1;
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TMR_OCInitStructure.TMR_OutputState = TMR_OutputState_Enable;
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TMR_OCInitStructure.TMR_Pulse = pulse;
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TMR_OCInitStructure.TMR_OCPolarity = TMR_OCPolarity_High;
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if(channel == 1)
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{
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TMR_OC1Init(TMRx, &TMR_OCInitStructure);
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TMR_OC1PreloadConfig(TMRx, TMR_OCPreload_Enable);
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}
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else if(channel == 2)
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{
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TMR_OC2Init(TMRx, &TMR_OCInitStructure);
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TMR_OC2PreloadConfig(TMRx, TMR_OCPreload_Enable);
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}
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else if(channel == 3)
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{
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TMR_OC3Init(TMRx, &TMR_OCInitStructure);
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TMR_OC3PreloadConfig(TMRx, TMR_OCPreload_Enable);
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}
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else if(channel == 4)
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{
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TMR_OC4Init(TMRx, &TMR_OCInitStructure);
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TMR_OC4PreloadConfig(TMRx, TMR_OCPreload_Enable);
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}
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TMR_ARPreloadConfig(TMRx, ENABLE);
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#if defined (SOC_SERIES_AT32F415)
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if(TMRx == TMR1)
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#else
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if(TMRx == TMR1 || TMRx == TMR8)
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#endif
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{
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TMR_CtrlPWMOutputs(TMRx,ENABLE);
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}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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TMR_Type *TMRx = (TMR_Type *)device->parent.user_data;
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return drv_pwm_enable(TMRx, configuration, RT_TRUE);
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case PWM_CMD_DISABLE:
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return drv_pwm_enable(TMRx, configuration, RT_FALSE);
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case PWM_CMD_SET:
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return drv_pwm_set(TMRx, configuration);
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case PWM_CMD_GET:
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return drv_pwm_get(TMRx, configuration);
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default:
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return RT_EINVAL;
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}
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}
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static int rt_hw_pwm_init(void)
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{
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int i = 0;
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int result = RT_EOK;
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for(i = 0; i < sizeof(at32_pwm_obj) / sizeof(at32_pwm_obj[0]); i++)
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{
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if(rt_device_pwm_register(&at32_pwm_obj[i].pwm_device, at32_pwm_obj[i].name, &drv_ops, at32_pwm_obj[i].tim_handle) == RT_EOK)
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{
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LOG_D("%s register success", at32_pwm_obj[i].name);
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}
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else
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{
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LOG_D("%s register failed", at32_pwm_obj[i].name);
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result = -RT_ERROR;
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_pwm_init);
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